Patents by Inventor Manjul Bhushan
Manjul Bhushan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9194909Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.Type: GrantFiled: March 2, 2012Date of Patent: November 24, 2015Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Patent number: 9110777Abstract: A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.Type: GrantFiled: February 14, 2012Date of Patent: August 18, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Aditya Bansal, Manjul Bhushan, Keith A. Jenkins, Jae-Joon Kim, Barry P. Linder, Kai Zhao
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Patent number: 9075109Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.Type: GrantFiled: March 2, 2012Date of Patent: July 7, 2015Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Patent number: 8723528Abstract: A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors.Type: GrantFiled: May 10, 2011Date of Patent: May 13, 2014Assignee: International Business Machines CorporationInventors: Mark B. Ketchen, Manjul Bhushan
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Patent number: 8589842Abstract: An approach for performing device-based random variability modeling in timing analysis of a digital integrated circuit having a gate-level design and a device-level custom design is described. In one embodiment, an algorithm is derived from results of simulating the operational behavior of a representative digital integrated circuit. A timing analysis is performed on the device-level custom design part of the digital integrated circuit to obtain device-level random variability sensitivity values. A gate-level characterization is performed on the gate-level design part of the digital integrated circuit to obtain logic gate random variability sensitivity values. A timing analysis is performed on the digital integrated circuit as a function of both the device-level random variability sensitivity values and the logic gate random variability sensitivity values.Type: GrantFiled: November 9, 2012Date of Patent: November 19, 2013Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Eric J. Fluhr, Stephen G. Shuma, Debjit Sinha, Chandramouli Visweswariah, James D. Warnock, Michael H. Wood
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Publication number: 20130212414Abstract: A system has at least a first circuit portion and a second circuit portion. The first circuit portion is operated at normal AC frequency. The second circuit portion is operated in a back-up mode at low AC frequency, such that the second circuit portion can rapidly come-online but has limited temperature bias instability degradation. The second circuit portion can then be brought on-line and operated at the normal AC frequency. A system including first and second circuit portions and a control unit, as well as a computer program product, are also provided.Type: ApplicationFiled: February 14, 2012Publication date: August 15, 2013Applicant: International Business Machines CorporationInventors: Aditya Bansal, Manjul Bhushan, Keith A. Jenkins, Jae-Joon Kim, Barry P. Linder, Kai Zhao
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Patent number: 8456169Abstract: A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.Type: GrantFiled: January 13, 2010Date of Patent: June 4, 2013Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Qingqing Liang, Edward P. Maciejewski
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Publication number: 20120286796Abstract: A structure and method is provided for testing a 2-dimensional array of electrical devices, such as a 2-dimensional array in the first metal level (M1) of an electronic structure. The method for testing the 2-dimensional array provides a parallel test approach. The test structure provides a plurality of test pad structures to implement the parallel test approach. The test pad structures may include field effect transistors.Type: ApplicationFiled: May 10, 2011Publication date: November 15, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Mark B. Ketchen, Manjul Bhushan
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Patent number: 8310269Abstract: A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.Type: GrantFiled: August 20, 2009Date of Patent: November 13, 2012Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen
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Publication number: 20120256651Abstract: An integrated test circuit includes pads of a padset for testing multiple device under test units (MDUTs). The MDUTs each include devices under test (DUTs). A first integrated test circuit metal layer is patterned to connect the pads to N MDUTs such that a first set of pads are employed for enabling testing of each MDUT and a second set of pads are designated for testing individual DUTs associated with the enabled MDUTs such that N parallel tests may be concurrently performed.Type: ApplicationFiled: April 8, 2011Publication date: October 11, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: MANJUL BHUSHAN, Mark B. Ketchen
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Patent number: 8248094Abstract: A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.Type: GrantFiled: August 20, 2009Date of Patent: August 21, 2012Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen
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Publication number: 20120166898Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (Ml) in the integrated circuit device.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Publication number: 20120161807Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Patent number: 8179120Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each including two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.Type: GrantFiled: August 20, 2009Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Patent number: 8027797Abstract: Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.Type: GrantFiled: April 28, 2008Date of Patent: September 27, 2011Assignee: International Business Machines CorporationInventors: Manjul Bhushan, Mark B. Ketchen, Dale J. Pearson
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Publication number: 20110169499Abstract: A test structure is provided that utilizes a time division sampling technique along with a statistical modeling technique that uses metal-oxide-semiconductor field effect transistor (MOSFET) saturation and linear characteristics to measure the mean (average) and sigma (statistical characterization of the variation) of a large population of electrical characteristics of electrical devices (e.g., integrated circuits) at high speed. Such electrical characteristics or sampling parameters include drive currents, leakage, resistances, etc.Type: ApplicationFiled: January 13, 2010Publication date: July 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen, Qingqing Liang, Edward P. Maciejewski
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Publication number: 20110043215Abstract: A test structure for an integrated circuit device includes one or more experiments selectively configured to receive one or more high-speed input signals as inputs thereto and to output at least one high-speed output signal therefrom, the one or more experiments each comprising two or more logic gates configured to determine differential delay characteristics of individual circuit devices, at a precision level on the order of picoseconds to less than 1 picosecond; and wherein the one or more sets of experiments are disposed, and are fully testable, at a first level of metal wiring (M1) in the integrated circuit device.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen, Chin Kim
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Publication number: 20110043243Abstract: A test system for determining leakage of an integrated circuit (IC) under test includes a test circuit formed on a same chip as the IC, the test circuit further having pulse generator configured to generate a high-speed input signal to the IC at a plurality of selectively programmable duty cycles and frequencies, the IC powered from a first power source independent from a second power source that powers the pulse generator; and a current measuring device configured to measure leakage current through the IC in a quiescent state, and current through the IC in an active switching state, responsive to the high-speed input signal at a plurality of the programmable duty cycles and frequencies, and wherein the test circuit utilizes only external low-speed input and output signals with respect to the chip.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen
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Publication number: 20110043242Abstract: A test structure for gathering switching history effect statistics includes a waveform generator circuit that selectively generates a first test waveform representative of a 1SW transistor switching event, and a second test waveform representative of a 2SW transistor switching event; and a history element circuit coupled to the waveform generator circuit, the history element circuit including a device under test (DUT) therein, and a variable delay chain therein, wherein a selected one of the first and second test waveforms are input to the DUT and the variable delay chain; wherein the history element circuit determines fractional a change in signal propagation delay through the DUT between the 1SW and 2SW transistor switching events, with the fractional change in signal propagation delay calibrated with timing measurements of a variable frequency ring oscillator; and wherein the test structure utilizes only external low-speed input and output signals with respect to a chip.Type: ApplicationFiled: August 20, 2009Publication date: February 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Manjul Bhushan, Mark B. Ketchen
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Publication number: 20090271134Abstract: Techniques for inline measurement of a switching history time constant in an integrated circuit device are provided. A series of pulses is launched into a first stage of a delay chain comprising a plurality of delay stages connected in series and having a length greater than a decay length of at least an initial one of the series of pulses, such that the at least initial one of the series of pulses does not appear at a second stage of the delay chain. An amount of time between the launching of the initial one of the series of pulses and the appearance of at least one of the series of pulses at the second stage of the delay chain is determined. The switching history time constant is calculated as a function of a number of stages traversed by the at least one pulse, the determined amount of time, and the decay length of the at least initial one of the series of pulses based at least in part on a switching history of the integrated circuit device.Type: ApplicationFiled: April 28, 2008Publication date: October 29, 2009Inventors: Manjul Bhushan, Mark B. Ketchen, Dale J. Pearson