Abstract: An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

Abstract: An integrated circuit device and device parameter characterization method are provided. The integrated circuit device has a padset with plurality of pads. The integrated circuit device also includes one or more arrays of devices under test, each of the one or more arrays disposed between two of the plurality of pads. The integrated circuit device further includes one or more n-bit decoders, each disposed between two of the plurality of pads and electrically coupled to a corresponding one of the one or more arrays. Each n-bit decoder comprises one or more outputs that deliver a defined voltage to each device under test in the corresponding one of the one or more arrays of devices under test. The integrated circuit device and corresponding electrical connections are implemented in a single level of metal.

Abstract: An integrated circuit device is provided including at least one first array configuration of integrated circuit components comprising a m×n array of FETs, without specified internal connections between the integrated circuit components, wherein m is greater than two. The integrated circuit device further includes at least one second array configuration of integrated circuit components comprising an array of integrated circuit components nominally identical to those of the first array configuration, with specified internal connections between integrated circuit components. A variation coefficient is determined for the integrated circuit components based on a measured specified parameter of the first array configuration and the second array configuration.

Abstract: A method for inline characterization of at least one high speed operating margin of a storage element is provided. An output of at least one latch of the integrated circuit device is transitioned from a first output logic state to a second output logic state. The storage element is accessed at least once in response to the transition of the output of the at least one latch to perform at least one of a write operation and a read operation. A state of at least one output latch is observed corresponding to a state of the storage element. The transitioning, accessing and observing steps are repeated for one or more adjustable parameters to determine at least one high speed operating margin of the storage element.

Abstract: Techniques for inline measurement of switching delay history effects in an integrated circuit device are provided. A pulse is launched down a delay chain. The pulse is substantially synchronized with a signal of a ring oscillator. The delay chain and the ring oscillator comprise substantially identical gates to a defined point on the ring oscillator corresponding to a far end of the delay chain. At least one difference in a number of gates traversed by an edge of the signal in the ring oscillator and a number of gates traversed by a corresponding edge of the pulse in the delay chain is measured when the pulse reaches the far end of the delay chain. One or more switching histories in the integrated circuit device are determined in accordance with the at least one measured difference in the number of gates traversed by an edge of the signal and a corresponding edge of the pulse.

Abstract: A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: A method for inline characterization of at least one high speed operating margin of a storage element is provided. An output of at least one latch of the integrated circuit device is transitioned from a first output logic state to a second output logic state. The storage element is accessed at least once in response to the transition of the output of the at least one latch to perform at least one of a write operation and a read operation. A state of at least one output latch is observed corresponding to a state of the storage element. The transitioning, accessing and observing steps are repeated for one or more adjustable parameters to determine at least one high speed operating margin of the storage element.

Abstract: An integrated circuit device having at least one fuse capable of being blown in order to provide measurements of fuse current-voltage characteristics is provided. The integrated circuit device also provides at least one pulse generation circuit associated with the fuse and capable of generating a pulse to blow the fuse through one or more DC input signals.

Abstract: An integrated circuit device is provided having a reference ring oscillator circuit having a plurality of stages. Each stage has a logic gate and electrically connecting to a first independent voltage source. The integrated circuit device also has at least one additional ring oscillator circuit having a plurality of stages. Each stage has a logic gate substantially identical to the logic gates of the reference ring oscillator circuit and electrically connecting to a respective at least one second independent voltage source. Each stage also has a FET load driven by the logic gate and electrically connecting to a third independent voltage source. A measured difference in capacitance between the reference ring oscillator circuit per stage and the at least one additional ring oscillator circuit per stage comprises a gate capacitance of a FET load.

Abstract: A method of measuring variability of integrated circuit components is provided. A specified parameter of at least one first array configuration comprising a plurality of the integrated circuit components without specified internal connections between the integrated circuit components is measured. The specified parameter of at least one second array configuration comprising a plurality of the integrated circuit components nominally identical to those of the first array configuration with specified internal connections between the integrated circuit components is also measured. A variation coefficient is determined for the integrated circuit components based on the measured specified parameter of the at least one first array configuration and the at least one second array configuration.

Abstract: An integrated circuit device is provided having one or more pairs of ring oscillator circuits. Each ring oscillator circuit of the one or more pairs of ring oscillator circuits is configured to connect to at least one voltage source capable of applying a stress to a ring oscillator circuit. One or more frequency measurement circuits are each electrically connected to a respective pair of the one or more pairs of ring oscillator circuits. Each frequency measurement circuit is configured to measure a stress induced change in frequency difference of the respective pair of the one or more pairs of ring oscillator circuits.

Abstract: An integrated circuit device is provided having a reference ring oscillator circuit having a plurality of stages. Each stage has a logic gate and electrically connecting to a first independent voltage source. The integrated circuit device also has at least one additional ring oscillator circuit having a plurality of stages. Each stage has a logic gate substantially identical to the logic gates of the reference ring oscillator circuit and electrically connecting to a respective at least one second independent voltage source. Each stage also has a FET load driven by the logic gate and electrically connecting to a third independent voltage source. A measured difference in capacitance between the reference ring oscillator circuit per stage and the at least one additional ring oscillator circuit per stage comprises a gate capacitance of a FET load.

Abstract: A method and apparatus is provided for measuring alternating current (AC) and direct current (DC) characteristics of a plurality of semiconductor devices. A ring oscillator generates pulses to drive the plurality of semiconductor devices under test. Current/Voltage (IV) and transfer characteristics of the plurality of semiconductor devices are measured using only DC input/output.

Abstract: An integrated circuit device is provided having one or more pairs of ring oscillator circuits. Each ring oscillator circuit of the one or more pairs of ring oscillator circuits is configured to connect to at least one voltage source capable of applying a stress to a ring oscillator circuit. One or more frequency measurement circuits are each electrically connected to a respective pair of the one or more pairs of ring oscillator circuits.