Patents by Inventor Manny K. F. Ma
Manny K. F. Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7903379Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: GrantFiled: July 31, 2007Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Michael D. Chaine, Manny K. F. Ma
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Patent number: 7253064Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: GrantFiled: May 25, 2004Date of Patent: August 7, 2007Assignee: Micron Technology, Inc.Inventors: Michael D. Chaine, Manny K. F. Ma
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Patent number: 6924522Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.Type: GrantFiled: May 21, 2002Date of Patent: August 2, 2005Assignee: Micron Technology, Inc.Inventors: Manny K. F. Ma, Yauh-Ching Liu
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Publication number: 20040219760Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: ApplicationFiled: May 25, 2004Publication date: November 4, 2004Applicant: Micro Technology, Inc.Inventors: Michael D. Chaine, Manny K.F. Ma
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Patent number: 6809386Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: GrantFiled: August 29, 2002Date of Patent: October 26, 2004Assignee: Micron Technology, Inc.Inventors: Michael D. Chaine, Manny K. F. Ma
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Publication number: 20040041215Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: ApplicationFiled: August 29, 2002Publication date: March 4, 2004Applicant: Micron Technology, Inc.Inventors: Michael D. Chaine, Manny K.F. Ma
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Patent number: 6699734Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.Type: GrantFiled: January 31, 2003Date of Patent: March 2, 2004Assignee: Micron Technology, Inc.Inventors: Aaron Schoenfeld, Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
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Patent number: 6600215Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.Type: GrantFiled: April 2, 1998Date of Patent: July 29, 2003Assignee: Micron Technology, Inc.Inventors: Aaron Schoenfeld, Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
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Patent number: 6586290Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.Type: GrantFiled: June 15, 1998Date of Patent: July 1, 2003Assignee: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
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Publication number: 20030113953Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.Type: ApplicationFiled: January 31, 2003Publication date: June 19, 2003Inventors: Aaron Schoenfeld, Manny K.F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
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Patent number: 6579746Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.Type: GrantFiled: August 17, 2001Date of Patent: June 17, 2003Assignee: Micron Technology, Inc.Inventors: Aaron Schoenfeld, Manny K. F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen
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Patent number: 6507074Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.Type: GrantFiled: August 30, 2001Date of Patent: January 14, 2003Assignee: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny K. F. Ma, Joseph C. Sher
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Patent number: 6504396Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.Type: GrantFiled: September 17, 2001Date of Patent: January 7, 2003Assignee: Micron Technology, Inc.Inventors: Joseph C. Sher, Manny K. F. Ma
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Publication number: 20020135005Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.Type: ApplicationFiled: May 21, 2002Publication date: September 26, 2002Applicant: Micron Technology, Inc.Inventors: Manny K. F. Ma, Yauh-Ching Liu
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Patent number: 6391755Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.Type: GrantFiled: July 27, 1999Date of Patent: May 21, 2002Assignee: Micron Technology, Inc.Inventors: Manny K. F. Ma, Yauh-Ching Liu
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Publication number: 20020047165Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.Type: ApplicationFiled: August 30, 2001Publication date: April 25, 2002Applicant: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny K.F. Ma, Joseph C. Sher
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Publication number: 20020030511Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.Type: ApplicationFiled: September 17, 2001Publication date: March 14, 2002Inventors: Joseph C. Sher, Manny K.F. Ma
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Patent number: 6356250Abstract: A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.Type: GrantFiled: August 16, 2000Date of Patent: March 12, 2002Assignee: Micron Technology, Inc.Inventors: David A. Cathey, Glen E. Hush, Manny K. F. Ma, Craig M. Dunham, David A. Zimlich
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Publication number: 20020009831Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices.Type: ApplicationFiled: July 27, 1999Publication date: January 24, 2002Inventors: MANNY K.F. MA, YAUH-CHING LIU
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Publication number: 20010052638Abstract: A method and apparatus for coupling a semiconductor die to terminals of a die package in which the die is housed. The apparatus comprises a die having first and second terminals. A first conductive member is elongated between a first end portion and a second end portion thereof such that the second end portion is proximate to the first terminal. A second conductive member is elongated between a first end portion and second end portion thereof such that the second end portion of the second conductive member is proximate to the second terminal of the die and the second conductive member is generally parallel to the first conductive member. The second end portions of the first and second conductive members may be coupled with conductive couplers to the first and second die terminals, respectively. The conductive members and conductive couplers may be sized and shaped to produce a selected capacitance and/or a selected impedance at the die terminals.Type: ApplicationFiled: August 17, 2001Publication date: December 20, 2001Inventors: Aaron Schoenfeld, Manny K.F. Ma, Larry D. Kinsman, J. Mike Brooks, Timothy J. Allen