Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: A field emission display includes electrostatic discharge protection circuits coupled to an emitter substrate and an extraction grid. In the preferred embodiment, the electrostatic discharge circuit includes diodes reverse biased between grid sections and a first reference potential or between row lines and a second reference potential. The diodes provide a current path to discharge static voltage and thereby prevent a high voltage differential from being maintained between the emitter sets and the extraction grids. The diodes thereby prevent the emitter sets from emitting electrons at a high rate that may damage or destroy the emitter sets. In one embodiment, the diodes are coupled directly between the grid sections and the row lines. In one embodiment, the diodes are formed in an insulative layer carrying the grid sections. In another embodiment, the diodes are integrated into the emitter substrate.

Abstract: An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.

Abstract: A buffer with an adjustable slew rate, including a current driver having an input terminal and an enable circuit connected to the input terminal to selectively enables the current driver. In one embodiment, the current driver includes an input terminal and the enable circuit includes a memory element, the state of which is used to activate the enable signal, a read circuit which reads the state of the memory element, a latch which latches the signal from the read circuit, and an output circuit connected to the input terminal of the current driver which provides a signal which selectively enables the current driver to adjust the slew rate.

Abstract: A circuit for providing electrostatic discharge (ESD) protection is disclosed. The circuit comprises a pair of CMOS field effect pull up and pull down transistors with reduced resistance source and drain, having a well resistor formed external to them between supply and ground busses respectively. During an ESD event, the well resistors serve to both limit the current flow through the transistors, and reduce the voltage drop across them.

Abstract: A memory device is described which includes a voltage regulator having a low power standby mode. A voltage regulator control circuit is described which places the voltage regulator in a high current mode when the outputs of the memory device are active. The regulator control circuit is operated in response to a combination of RAS*, CAS* and OE* signals.

Abstract: A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second circuit portion. Control circuitry generates a first powerup control signal. A first switch couples the supply voltage to the first circuit portion based on the first powerup control signal being active. The first powerup control signal is delayed by a selected time delay to produce a second powerup control signal. Alternatively, the second powerup control signal is generated independent of the first powerup control signal, but is active the selected time delay after the first powerup control signal is active. A second switch couples the supply voltage to the second circuit portion based on the second powerup control signal being active.

Abstract: A voltage compensating CMOS input buffer converts input TTL signals to CMOS logic levels, and compensates for changing supply voltage by using a n-channel transistor to vary the effective size ratio of pairs p-channel to n-channel transistors making up an input inverter. The compensating transistor becomes operable with increasing supply voltage to help the n-channel input inverter transistors offset the p-channel input inverter transistors whose trip points would otherwise have been increased by increasing power supply voltage. As the power supply voltage decreases, the compensating transistor turns off, returning the input inverter to its original size ratio. The gate of the compensating transistor is coupled to the supply voltage through two diodes to control the amount of current flowing through the compensating transistor. Further trip point transistors in series with the compensating transistor have their gates coupled to the input signals to help stabilize the trip points.

Abstract: A complementary metal-oxide semiconductor (CMOS) integrated circuit, such as a dynamic random access memory (DRAM), is powered by supply voltage. The CMOS integrated circuit is divided into n circuit portions including a first circuit portion and a second circuit portion. Control circuitry generates a first powerup control signal. A first switch couples the supply voltage to the first circuit portion based on the first powerup control signal being active. The first powerup control signal is delayed by a selected time delay to produce a second powerup control signal. Alternatively, the second powerup control signal is generated independent of the first powerup control signal, but is active the selected time delay after the first powerup control signal is active. A second switch couples the supply voltage to the second circuit portion based on the second powerup control signal being active.

Abstract: A super-voltage circuit with a fast reset capability is formed in an integrated circuit for generating a test mode logic state for testing other circuits in the same integrated circuit. The super-voltage circuit includes a sensing circuit, a reset circuit, and an output circuit connected to both the sensing circuit and the reset circuit. When the input voltage receives a super-voltage which is higher than either the logic high or low voltages, the sensing circuit generates at its output a high voltage. The reset circuit also receiving the same input voltage as the sensing circuit generates at its output a logic low state when the input voltage is at the super-voltage or logic high voltage. When the sensing circuit is generating the high voltage and the reset circuit is generating the logic low state the output circuit generates at its output a logic low voltage. The logic low voltage signifies that the integrated circuit is now in the super-voltage test mode.

Abstract: Circuits to convert an input voltage supply to an output voltage supply having a different magnitude or polarity. The circuits include a capacitor having a first terminal and a second terminal, a first switch coupled to the first terminal of the capacitor, and a second switch. The circuits further include a first node coupled between the second terminal of the capacitor and the second switch, and a third switch having a first terminal coupled to the first node and a second terminal coupled to a second node. The first switch is adapted to couple the first terminal of the capacitor to the input supply voltage during a fill state and a second voltage level during a dump state. The second switch is adapted to couple the first node to a third voltage level during the fill state and present a high impedance to the first node during the dump state. The third switch is adapted to dump a charge from the first node to the second node during the dump state, thereby producing an output voltage at the second node.

Abstract: A least one one-time programmable nonvolatile (NV) memory element uses a field-effect transistor (FET) as a selectively programmed element. A short duration applied drain voltage exceeding the FET's drain-to-source breakdown voltage results in a drain source resistance which is substantially unaffected by the voltages typically applied at the gate terminal. Since the programmed resistance is less than 200 ohms and a high programming voltage is not required, the present invention compares favorably with antifuse nonvolatile memory techniques. The nonvolatile memory element is implemented without adding complexity to a very large scale integrated (VLSI) circuit process.

Abstract: A signal isolation and decoupling structure fabricated in an integrated circuit device for providing signal isolation and decoupling for signal carrying conductors of the integrated circuit device, wherein one of the conductors is embedded in dielectric material and enclosed within an isolation structure of an electrically conductive material which is formed in the integrated circuit device and extends substantially the length of the conductor, the isolation structure including top and bottom walls of electrically conductive material and first and side walls, also of an electrically conductive material, which electrically interconnect the top and bottom walls, forming an enclosure around the conductor. Also described is a method for fabricating the isolation structure in the integrated circuit device.

Abstract: A frequency adjustable, zero temperature coefficient referencing ring oscillator circuit includes a plurality of inverter stages each having a switching circuit that produces the oscillating output signal for the ring oscillator circuit and a control circuit that controls the switching circuit to establish the frequency of the output signal, the control circuit including field-effect transistors which are operated as output resistance controllable devices and which have their operating points, and thus their output resistances, established by a reference voltage that is produced by a precision reference voltage generating circuit so that the operating frequency of the ring oscillator circuit can be set by adjusting the value of the reference signals produced by the precision reference signal generating circuit and is maintained at the setpoint value because the precision reference voltage generating circuit operates independently of variations in temperature and/or the power supply voltage.

Abstract: The present invention relates to methods and apparatus for manufacturing semiconductor devices, and in particular for forming electrostatic discharge (ESD) protection devices, using selective siliciding, in a CMOS integrated circuit. Predetermined discharge paths are created for discharging input and output buffer pads, during an ESD event, through ESD protection devices. During fabrication, an oxide layer is utilized as a mask to prevent silicided regions from forming in source/drain regions, self-aligned with the gates. The buffer transistor gate-to-contact spacing is made longer than the gate-to-contact spacing in the associated protection transistor, to shunt charge through the protection device. In a further embodiment, active area resistance is formed between the output/input buffer transistor and the ESD protection device, to further increase the resistance of the path between the buffer pad to the associated buffer transistor.

Abstract: The present invention teaches fabrication of a high-resistance integrated circuit diffusion resistor that uses standard CMOS process steps. By appropriate masking during ion-implantation of source/drain diffusion regions, diffusion resistors created during NMOS source/drain implant may be counterdoped during PMOS source/drain implants and vice-versa. By appropriate choice of relative concentrations of a resistor dopant and counterdopant, and choice of diffusion depths, junction diodes can be formed which create a pinched resistor by constricting the current flow. The relative dopant concentrations can also be chosen to create regions of light effective doping within the diffusion resistor rather than creating junction diodes.

Abstract: An electrostatic discharge protection system for an integrated circuit device, such as a solid state memory device or any other integrated circuit device having a plurality of individual power groups, includes a loop of an electrically conductive material that is disposed on the device defining a electrostatic discharge path portion, a plurality of first punch-through devices which connect the input/output pins of different power groups of the integrated circuit device to the power sources of the associated power group, and a plurality of second punch-through devices which connect all of the input/output pins of the integrated circuit device to the electrostatic discharge path portion, thereby providing a discharge path that is common to all of the power groups of the integrated circuit device.

Abstract: A floating gate transistor is formed by simultaneously creating buried contact openings on both EEPROM transistor gates and DRAM access transistor source/drain diffusions. Conventional DRAM process steps are used to form cell storage capacitors in all the buried contact openings, including buried contact openings on EEPROM transistor gates. An EEPROM transistor gate and its associated cell storage capacitor bottom plate together forms a floating gate completely surrounded by insulating material. The top cell storage capacitor plate on an EEPROM transistor is used as a control gate to apply programming voltages to the EEPROM transistor. Reading, writing, and erasing the EEPROM element are analogous to conventional floating-gate tunneling oxide (FLOTOX) EEPROM devices. In this way, existing DRAM process steps are used to implement an EEPROM floating gate transistor nonvolatile memory element.