Patents by Inventor Manny Ma
Manny Ma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20080019064Abstract: A cascode I/O driver is described that includes a barrier formed in the shared region between the two transistors. The barrier region allows the I/O driver to be designed to primarily meet I/O requirements. Accordingly, improved operating speeds are achieved. An system is described that includes an I/O driver in parallel with an ESD device. In an embodiment, the I/O driver may assist the ESD device in discharging electrostatic, after the ESD begins conducting.Type: ApplicationFiled: July 31, 2007Publication date: January 24, 2008Inventors: Michael Chaine, Manny Ma
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Patent number: 6653220Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: August 3, 2001Date of Patent: November 25, 2003Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6524922Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.Type: GrantFiled: September 28, 2000Date of Patent: February 25, 2003Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 6518178Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.Type: GrantFiled: September 28, 2000Date of Patent: February 11, 2003Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 6444572Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.Type: GrantFiled: May 21, 2001Date of Patent: September 3, 2002Assignee: Micron Technology Inc.Inventors: Zhiqiang Wu, Alan R. Reinberg, Manny Ma
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Patent number: 6444577Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.Type: GrantFiled: July 12, 1999Date of Patent: September 3, 2002Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Publication number: 20020004297Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: ApplicationFiled: August 3, 2001Publication date: January 10, 2002Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6316976Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.Type: GrantFiled: April 28, 2000Date of Patent: November 13, 2001Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld, Manny Ma, R. Jacob Baker
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Publication number: 20010023131Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.Type: ApplicationFiled: May 21, 2001Publication date: September 20, 2001Inventors: Zhiqiang Wu, Alan R. Reinberg, Manny Ma
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Patent number: 6281109Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: May 15, 2000Date of Patent: August 28, 2001Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6274482Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.Type: GrantFiled: April 1, 1999Date of Patent: August 14, 2001Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Alan R. Reinberg, Manny Ma
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Patent number: 6069506Abstract: A method and apparatus for improving the performance and accuracy of a digital delay locked loop (DDLL) by using a unique correction latch and novel reset mechanism circuit for eliminating DDLL minimum and maximum delay states of inoperability. The accuracy of a DDLL is further improved by the use of a three-NAND gate logic delay element design. A DDLL according to the present invention provides symmetrical rising and falling edges of the signal at the output of each delay line element. A DDLL according to the present invention further ensures insensitivity to random values upon initialization. In addition, a DDLL according to the present invention has increased accuracy due to ensuring a comparison between the actual, not divided-down, input signal and an output signal during a phase detect operation.Type: GrantFiled: May 20, 1998Date of Patent: May 30, 2000Assignee: Micron Technology, Inc.Inventors: James E. Miller, Jr., Aaron Schoenfeld, Manny Ma, R. Jacob Baker
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Patent number: 6066548Abstract: An exemplary implementation of the present invention includes a method for forming conductive lines fabricated in a semiconductor device, the method comprising the steps of forming a first layer of patterned conductive lines, having substantially vertical sidewalls, on a supporting material; of forming insulative spacers about the substantially vertical sidewalls; of forming trenches into the supporting material that align to the insulative spacers; and of forming a second layer of patterned conductive lines such that each line is at least partially embedded within a corresponding trench. Preferably, the conductive lines, formed by a double metal process, are recessed into a supporting material that has a substantially planar surface.Type: GrantFiled: October 31, 1996Date of Patent: May 23, 2000Assignee: Micron Technology, Inc.Inventors: Manny Ma, Trung Doan, Jeff Zhiqiang Wu
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Patent number: 6040733Abstract: An electrostatic discharge (ESD) protection circuit includes two stages. A first stage is operatively coupled to a metal bonding pad. This first stage is an npn transistor having a low resistance fusible element which has a fast response time. A second stage is operatively coupled in series to the first stage. The second stage provides a high-resistance path to protect the npn transistor after the fusible element has fused to into a high resistance voltage path. In addition, a semiconductor device having internal circuitry protected by this two stage ESD protection circuit is provided. The ESD protection circuit is operatively coupled between the bonding pad which is located external to the semiconductor device and the internal circuitry.Type: GrantFiled: July 17, 1998Date of Patent: March 21, 2000Assignee: Micron Technology, Inc.Inventors: Stephen L. Casper, Manny Ma
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Patent number: 5985766Abstract: The invention provides methods for forming contact openings to a substrate location with which electrical connection is desired. According to one aspect, a multi-level layer comprising masking material or photoresist is formed atop an electrically conductive substrate surface and defines a mask opening through which a contact opening is to be formed to an elevationally lower substrate location. A single layer of photoresist is patterned to form an elevationally thicker first layer immediately laterally adjacent the mask opening than a second layer which is formed laterally outward of the first layer. The electrically conductive substrate surface is etched through the mask opening to form the contact opening. The photoresist second layer is removed and the conductive substrate surface is etched to form a portion of an outer conductive component. Thereafter, conductive material is formed in the contact opening to electrically connect elevationally separated layers.Type: GrantFiled: February 27, 1997Date of Patent: November 16, 1999Assignee: Micron Technology, Inc.Inventors: Zhiqiang Wu, Alan R. Reinberg, Manny Ma
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Patent number: 5976915Abstract: A packaged semiconductor device, such as a lead frame device, includes a circuit supported within an enclosure. The circuit is coupled to a plurality of conductive leads within the enclosure. The leads extend from the enclosure for electrically coupling the circuit to external circuitry. At least one of the leads is shielded to reduce inductive coupling and crosstalk between the leads during high frequency switching. The shielded lead has a conductive base, a non-conductive layer disposed on the base, and a conductive layer disposed on the non-conductive layer. The non-conductive and conductive layers may be formed prior to electrically coupling the lead to the circuit, or following assembly of the lead frame package. The shielding may extend into the package enclosure, or may terminate external to the enclosure.Type: GrantFiled: November 30, 1998Date of Patent: November 2, 1999Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 5949114Abstract: A method of fabricating bipolar junction transistors particularly suitable for electrostatic discharge protection and high voltage MOSFETs. In accordance with the invention, a mask covers bird's beaks formed between field oxide layers and doped regions of a semiconductor substrate. A silicide layer is then added to the exposed surface of the doped regions. The mask prevents the silicide layer from overlying the bird's beaks, thereby precluding the silicide layer from degrading the breakdown junction voltage of the transistor.Type: GrantFiled: November 7, 1996Date of Patent: September 7, 1999Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 5885864Abstract: An exemplary embodiment of the present invention includes a memory cell in a semiconductor device, comprising a substantially vertical-gated, access transistor having its gate electrode surrounding a pillar portion of a silicon material, a first source/drain electrode in an upper portion of the pillar portion and a second source/drain electrode in a silicon material extending substantially horizontally about the base of the pillar portion; and a storage capacitor having its storage electrode connecting to the first source/drain electrode. The structure of the storage capacitor may configured as desired which includes a stacked capacitor structure or a cylindrical capacitor structure.Type: GrantFiled: October 24, 1996Date of Patent: March 23, 1999Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 5880520Abstract: A packaged semiconductor device, such as a lead frame device, includes a circuit supported within an enclosure. The circuit is coupled to a plurality of conductive leads within the enclosure. The leads extend from the enclosure for electrically coupling the circuit to external circuitry. At least one of the leads is shielded to reduce inductive coupling and crosstalk between the leads during high frequency switching. The shielded lead has a conductive base, a non-conductive layer disposed on the base, and a conductive layer disposed on the non-conductive layer. The non-conductive and conductive layers may be formed prior to electrically coupling the lead to the circuit, or following assembly of the lead frame package. The shielding may extend into the package enclosure, or may terminate external to the enclosure.Type: GrantFiled: March 31, 1998Date of Patent: March 9, 1999Assignee: Micron Technology, Inc.Inventor: Manny Ma
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Patent number: 5841723Abstract: A method and apparatus for programming anti-fuses using a positive voltage switching circuit for connecting an external terminal receiving a positive programming voltage to one plate of an anti-fuse responsive to an active program enable signal. A negative voltage switching circuit connects an external terminal receiving a negative programming voltage to the other plate of the anti-fuse responsive to the active program enable signal. The negative voltage switching circuit normally maintains one plate of the anti-fuse at ground potential when the anti-fuse is not being programmed so that its conductive state can be read by applying a voltage to the other plate of the anti-fuse. The transistors used in the negative voltage switching circuit are fabricated in a well that is isolated from the substrate in which the transistors in the positive voltage switching circuit are fabricated.Type: GrantFiled: March 24, 1998Date of Patent: November 24, 1998Assignee: Micron Technology, Inc.Inventor: Manny Ma