Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: Embodiments herein provide a testing apparatus (whether physical or simulated) for testing a non-core MMU in a processor chip. Unlike core MMUs, non-core MMUs may be located in a part of the processor chip outside of the processing cores in the chip. Instead of being used to perform address translation requests sent by the processing core, the non-core MMUs may be used by other hardware modules in the processor chip such as compression engines, crypto engines, accelerators, etc. In one embodiment, the testing apparatus includes a MMU testor that transmits the translation requests to the non-core MMU which tests its functionality. Using the data provided in the translation requests, the non-core MMU performs virtual to physical address translations. The non-core MMU transmits the results of these translations to the MMU testor which compares these results to expected results to identify any design flaws in the non-core MMU.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention can update the coverage schema, wherein updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generate constraints used to satisfy requirements for meeting the first and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated schema.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention includes updating the coverage schema, wherein the updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generating constraints used to satisfy requirements for meeting the first set of events and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated coverage schema.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: Embodiments disclose techniques for scheduling test cases without regeneration to verify and validate a computing system. In one embodiment, a testing engine generates a test case for a plurality of processors. Each test case includes streams of instructions. The testing engine also allocates at least one cache line associated with the streams of instructions of the generated test case such that each of the plurality of processors accesses different memory locations within the at least one cache line. The testing engine further schedules the generated test case for execution by the plurality of processors to achieve at least a first test coverage among the plurality of processors. The testing engine further re-schedules the generated test case for re-execution by the plurality of processors to achieve at least a second test coverage among the plurality of processors.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention includes updating the coverage schema, wherein the updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generating constraints used to satisfy requirements for meeting the first set of events and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated coverage schema.

Abstract: A mapping may be changed in a table stored in memory. The table may map a first set of addresses, for a set of data, to a second set of addresses. The changing of the mapping may including mapping the first set of addresses to a third set of addresses. In response to the changing of the mapping, one or more flush operations may be executed to invalidate one or more entries within one or more address translation caches. The one or more entries may include the second set of addresses. In response to the executing of the one or more flush operations, a first test case may be run. The first test case may be to test whether any of the first set of addresses are mapping to the second set of addresses.

Abstract: Data is replicated into a memory cache with non-naturally aligned data boundaries to reduce the time needed to generate test cases for testing a processor. Placing data in the non-naturally aligned data boundaries as described herein allows replicated testing of the memory cache while preserving double word and quad word boundaries in segments of the replicated test data. This allows test cases to be generated for a section of memory and then replicated throughout the memory and tested by a single test branching back and using the next strand of the replicated test data in the memory cache.

Abstract: Embodiments of the present invention provide methods, computer program products, and systems for generating comprehensive test cases covering new events yet to be covered. Embodiments of the present invention can be used to receive a request to generate a test case, wherein the request comprises a coverage schema associated with a first set of events to be covered in the generated test case. Embodiments of the present invention includes updating the coverage schema, wherein the updating the coverage schema comprises adding a second set of events to be covered in the generated test case and generating constraints used to satisfy requirements for meeting the first set of events and the second set of events in the updated coverage schema. Embodiments of the present invention can generate a test case using the generated constraints and the updated coverage schema.

Abstract: A method of testing cache coherency in a computer system design allocates different portions of a single cache line for use by accelerators and processors. The different portions of the cache line can have different sizes, and the processors and accelerators can operate in the simulation at different frequencies. The verification system can control execution of the instructions to invoke different modes of the coherency mechanism such as direct memory access or cache intervention. The invention provides a further opportunity to test any accelerator having an original function and an inverse function by allocating cache lines to generate an original function output, allocating cache lines to generate an inverse function output based on the original function output, and verifying correctness of the original and inverse functions by comparing the inverse function output to the original function input.

Abstract: Performance measurement of hardware accelerators, where one or more computer processors are operably coupled to at least one hardware accelerator, and a computer memory is operatively coupled to the one or more computer processors, including operating by the one or more processors the accelerator at saturation, submitting data processing tasks by the processors to the accelerator at a rate that saturates the data processing resources of the accelerator, causing the accelerator to decline at least some of the submitted tasks; and while the accelerator is operating at saturation, measuring by the processors accelerator performance according to a period of time during which the accelerator accepts a plurality of submitted tasks.

Abstract: Embodiments of the present invention disclose a method, computer program product, and system for verifying transitions between logical partition configurations. A computer system divides the physical resources of a processing core into logical partitions, each of which has at least one processing subcore. The computer system loads the contexts of the logical partitions and assigns test cases to each processing subcore. The processing subcore executes the test case, verifying the context of the logical partition. The computer system reassigns the test cases to different processing cores in anticipation of reconfiguring the number of logical partitions on the processing core. The computing system reconfigures the number of logical partitions on the processing core and executes the test cases as assigned on the reconfigured logical partitions.