Abstract: An asymmetric cladded conductor structure for a magnetic field sensitive memory cell is disclosed. One or both of the conductors that cross the memory cell can include an asymmetric cladding that covers a top surface and only a portion of the opposed side surfaces of the conductors such that the cladding on the opposed side surfaces is recessed along those opposed side surfaces in a direction away from a data layer of the memory cell. The cladding is recessed by an offset distance. The asymmetric cladding increases a reluctance of a closed magnetic path with a resulting decrease in magnetic coupling with the data layer. An aspect ratio of the memory cell can be reduced thereby increasing areal density.

Abstract: In one embodiment, a memory device includes a plurality of magnetic data cells and a magnetic reference cell extending uninterrupted along more than one of the plurality of data cells.

Abstract: A spin dependent tunneling (“SDT”) junction of a memory cell for a Magnetic Random Access Memory (“MRAM”) device includes a pinned ferromagnetic layer, followed by an insulating tunnel barrier and a sense ferromagnetic layer. During fabrication of the MRAM device, after formation of the pinned layer but before formation of the insulating tunnel barrier, an exposed surface of the pinned layer is flattened. The exposed surface of the pinned layer may be flattened by an ion etching process.

Abstract: A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed between the permeable metal layer and the magnetic memory array.

Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.

Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.

Abstract: A memory device having a cross point array of memory cells includes a temperature sensor and a reference memory cell. The temperature sensor senses the temperature of the memory device and data from the temperature sensor and the reference memory cell are used to update write currents used to program the array of memory cells. A method of calibrating the memory device involves detecting a temperature of the memory device, determining whether the temperature of the memory device has changed by a threshold value, and updating write current values if the temperature of the memory device changes by the threshold value. The write current values can be updated by data from the reference memory cell, or from write current values stored in a lookup table.

Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.

Abstract: A magnetic memory cell includes a first magneto-resistive device and a second magneto-resistive device. The first magneto-resistive device has a first sense layer. The second magneto-resistive device is connected in series with the first magneto-resistive device. The second magneto-resistive device has a second sense layer. At least one controlled nucleation site is placed on at least one of the first sense layer and the second sense layer.

Abstract: A magnetic memory includes a circuit configured to apply a reverse magnetic field to one or more half-selected magnetic memory cells to improve half-select margin in the magnetic memory.

Abstract: A magnetic random access memory module includes a magnetic memory array. A permeable metal layer extends over a first side of the magnetic memory array. An electrically insulating layer is disposed between the permeable metal layer and the magnetic memory array.

Abstract: A magnetic memory includes a circuit configured to apply a reverse magnetic field to one or more half-selected magnetic memory cells to improve half-select margin in the magnetic memory.

Abstract: A magnetic random access memory device uses toroid-like magnetic memory cells. An axial opening extends through each of the memory cells and is generally aligned along a first axis. A first conductor and a second conductor pass through the axial opening of each memory cell and are generally aligned with the first axis.

Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.

Abstract: A solid-state memory including an array of magnetic storage cells and a set of conductors. The process steps that pattern the conductors also patterns the magnetic layers in the magnetic storage cells thereby avoiding the need to employ precise alignment between pattern masks.

Abstract: A multibit magnetic memory cell includes first and second data layers. An antiferromagnetically coupled layer pair is disposed between the first and second data layers. In one embodiment the first and second data layers have distinct coercivities. The memory cell structure comprises a plurality of separation layers separating the first and second data layers and the antiferromagnetically coupled layer pair. In one embodiment, a coupling layer disposed between the antiferromagnetically coupled layer pair is a metallic conductive material comprising Ruthenium (Ru) or copper (Cu). In one embodiment, separation layers disposed between each of the first and second data layers and the antiferromagnetically coupled pair is nonconductive such that the cell is a spin dependent tunneling magnetoresistive (TMR) cell. Alternatively, the separation layers are conductive such that the cell is a giant magnetoresistive (GMR) cell. In various embodiments, a height of the first and second data layers is distinct.

Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.

Abstract: A write line structure for a magnetic memory cell includes a write conductor having a front surface facing the memory cell, a back surface and two sides surfaces. A cladding layer is disposed adjacent a portion of the front surface of the write conductor, with the cladding layer terminating at spaced first and second poles adjacent the front surface of the write conductor. A data storage layer is operatively positioned adjacent the cladding layer. The distance between the poles is less than the width of the write conductor. The width of the data storage layer may be greater than or less than the distance between the poles.

Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.

Abstract: A memory device includes a memory array having a substrate, an array of memory cells disposed over the substrate, row conductors coupled to the memory cells, and column conductors coupled to the memory cells. The memory device also includes current sources that generate variable write currents in response to temperature changes in the memory array. The variable write currents are generated to accommodate the change in coercivities of the memory cells as the temperature of the array changes. A current source can include a temperature sensor that provides a continuous, immediate output to the current sensor to ensure accurate adjustment of a write current generated by the current source. There is no need to halt operation of the memory device to calibrate the current source. In addition, the current source provides an accurate adjustment to the write current because the temperature used by the temperature sensor to generate the output may be taken contemporaneously with generation of the write current.