Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: In a described example, a method of forming a capacitor includes forming a doped polysilicon layer over a semiconductor substrate. The method also includes forming a dielectric layer on the doped polysilicon layer. The method also includes forming an undoped polysilicon layer on the dielectric layer.

Abstract: A method of fabricating an integrated circuit includes etching trenches in a first surface of a semiconductor layer. A trench dielectric layer is formed over the first surface and over bottoms and sidewalls of the trenches and a doped polysilicon layer is formed over the trench dielectric layer and within the trenches. The doped polysilicon layer is patterned to form a polysilicon bridge that connects to the polysilicon within the filled trenches and a blanket implant of a first dopant is directed to the polysilicon bridge and to the first surface. The blanket implant forms a contact region extending from the first surface into the semiconductor layer.

Abstract: In general, embodiments of the present invention provide methods, apparatus, systems, computing devices, computing entities, and/or the like for performing scalable dynamic data transmissions. Certain embodiments of the present invention utilize systems, methods, and computer program products that perform scalable dynamic data transmission using structured data responses that include structured response extensions, where the structured response extensions may include dynamic extension response fields generated based on a structured request header of a corresponding structured data request.

Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Abstract: Example embodiments of the present invention provide a method, an apparatus, and a computer program product for brokering establishment of a trusted relationship between a first domain and a second domain. The method includes receiving, from a first domain, a request to establish a trusted relationship with a second domain and brokering establishment of the trusted relationship between the first domain and the second. Other example embodiments include brokering authenticated access for a client in the first domain to a resource in the second domain according to the established trusted relationship.

Abstract: A method of fabricating an integrated circuit (IC) chip is disclosed. The method starts with opening a window on a first surface of the IC chip through a passivation overcoat to expose the copper metallization layer. The window has sidewalls and a bottom that is adjacent the copper metallization layer. The method continues with depositing a barrier conductive stack on the passivation overcoat and exposed portions of the copper metallization layer, then depositing a sacrificial conductive stack on the barrier conductive stack. The sacrificial conductive stack has a thickness between 50 ? and 500 ?. The first surface of the semiconductor chip is polished to remove the sacrificial conductive stack and the barrier conductive stack from the surface of the passivation overcoat.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract: An integrated circuit including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, with a solder ball formed on the self-aligned under bump metal pad. Processes of forming integrated circuits including a self-aligned under bump metal pad formed on a top metal interconnect level in a connection opening in a dielectric layer, by a process of forming one or more metal layers on the interconnect level and the dielectric layer, selectively removing the metal from over the dielectric layer, and subsequently forming a solder ball on the self-aligned under bump metal pad. Some examples include additional metal layers formed after the selective removal process, and may include an additional selective removal process on the additional metal layers.

Abstract: A system and method for enabling routing of data on a network based on a portion of data accessed from a non-network enabled device is disclosed. The technology includes a method for enabling routing of data on a network based on a portion of data accessed from a non-network enabled device. The method includes detecting a non-network enabled device locally coupled to a first computer system, the first computer system coupled to the network. The method further includes enabling routing of data through the non-network enabled device to a second computer system coupled to the network by using the first computer system as a communication interface between the non-network enabled device and the second computer system wherein the second computer system is automatically identified based on recognizing a portion of the data as a routing destination.

Abstract: Deposition of lead-zirconium-titanate (PZT) ferroelectric material over iridium metal, in the formation of a ferroelectric capacitor in an integrated circuit. The capacitor is formed by the deposition of a lower conductive plate layer having iridium metal as a top layer. The surface of the iridium metal is thermally oxidized, prior to or during the deposition of the PZT material. The resulting iridium oxide at the surface of the iridium metal is very thin, on the order of a few nanometers, which allows the deposited PZT to nucleate according to the crystalline structure of the iridium metal rather than that of iridium oxide. The iridium oxide is also of intermediate stoichiometry (IrO2-x), and reacts with the PZT material being deposited.

Abstract: An integrated circuit containing a FeCap array. The FeCap array is at least partially surrounded on the sides by hydrogen barrier walls and on the top by a hydrogen barrier top plate. A method for at least partially enclosing a FeCap array with hydrogen barrier walls and a hydrogen barrier top plate.