Abstract: Provided is a method for manufacturing an interconnect. The method for manufacturing the interconnect, in one embodiment, includes forming a first metal feature over or within a substrate, the first metal feature having an exposed surface. The method for manufacturing the interconnect may additionally include cleaning the exposed surface using a reactive system with a reducing agent, and subjecting the exposed surface to a plasma etch. The method for manufacturing the interconnect may further include contacting the first metal feature with a second metal feature.

Abstract: A fax account is described and creates an association between users and documents that are faxed. A fax account allows a user to secure their faxed documents and organize and streamline fax communication via different transports. In at least some embodiments, security is enhanced through the use of an authentication model that authenticates individual users before giving them access to the fax functionality or, more accurately, their fax account. In at least some embodiments, fax accounts also provide users with an infrastructure through which they can manage their documents. In addition, in at least some embodiments, fax accounts can be used to manage and direct received faxes to the intended recipient, thus reducing the possibility of an unintended recipient gaining access to the fax.

Abstract: Post chemical mechanical polishing (CMP) cleaning methods are disclosed which reduce integrated circuit defects. A corrosion inhibitor is preferably applied during the post-CMP cleaning steps after application of a first chemistry. Subsequent to the application of the corrosion inhibitor a rinsing step using deionized water is employed. In this manner, the corrosion inhibitor applied during the post-CMP clean fills voids created in previous passivation layers by previous chemistries. Also, existing post-CMP equipment may be used to implement the preferred embodiments of the present invention. Preferably the corrosion inhibitor applied during the post-CMP clean is benzotriazole (BTA).

Abstract: A method of constructing a semiconductor device 10 is disclosed which includes a reflow step. The device 10 comprises a conductive via 20 electrically connected to a conductive interconnect 28. The formation of interconnect 28 can result in damage to conductive via 20 including the removal of material within conductive via 20 to form a void 30. The metal reflow step involves heating the structure to a temperature short of the melting point of the conductive material forming the conductive via 20 and the conductive interconnect 28. The reflow step results in the migration of conductive material into the void 30 and a widening of the conductive interface between the conductive via 20 and the conductive interconnect 28.

Abstract: The present invention provides an improved process for controlling the absorbency and other properties of collagen flakes. The process comprises using freeze-dried collagen material and heating the freeze dried collagen material to a predetermined temperature range between 80 C. and 200 C. for a selected period of time. The collagen flakes will have an improved absorbency, density, porosity, and color. The color of the collagen flakes varies from white to brown. The porosity, absorbency, density and color of the collagen is selectively dependent upon the time and temperature used to heat the collagen flakes. The absorption of the collagen material is selected to be between two to twenty times the weight of the product, and the density of the collagen material is selected to be between 0.1 g/cc to 1.0 g/cc. The collagen flakes are ground into a powder after heating, for use as a wound dressing for medium to high exudative wounds.

Abstract: Improved collagen/synthetic resin foam wound dressings are provided which include a layer of synthetic resin foam (preferably polyurethane foam) together with a layer of freeze-dried collagen applied over and coupled with the resin foam layer. The collagen acts as an exudate absorber, in order to promote wound healing. The dressings are fabricated by first providing a resin foam layer, followed by depositing a collagen dispersion over the foam layer and freeze-drying the dispersion.

Abstract: A contact (160) is formed by depositing a conductive liner (130), treating the liner (130) with hydrogen, depositing a conductive barrier (140), and filling the contact hole (120) with a metal (150). Hydrogen treatment improves contact resistance and adhesion between the liner (130) and barrier (140). The hydrogen treatment may be a hydrogen plasma treatment and may be performed one or more times during contact formation such as after contact etch, after liner deposition, during liner anneal, after liner anneal, or after barrier deposition.

Abstract: A dielectric layer (110), such as an interlevel dielectric ILD or PMD, comprising a doped silicate glass layer (112) with an overlying CMP stopping layer (114). The CMP stopping layer (114) comprises a dielectric such as an undoped oxide. The CMP stopping layer (114) is resistant to dielectric erosion during a subsequent metal CMP step.

Abstract: An intermetal level dielectric with two different low dielectric constant insulators: one for gap filling (140) within a metal level and the other (150) for between metal levels. Preferred embodiments include HSQ (140) as the gap filling low dielectric constant insulator and fluorinated silicon oxide (150) as the between metal level low dielectric constant insulator.

Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.

Abstract: A semiconductor device is disclosed which uses an embedded pillar 38 to prevent damage (e.g. dishing, smearing, overetching) to damascene conductors during fabrication, particularly where such conductors are relatively large. The device comprises an insulating layer 22 formed on a substrate 20 and having a substantially planar upper surface with a plurality of channels 26, 34 formed therein. Channel 34 may be described as comprised of contiguous narrow channel segments (including right segment 40, top segment 41, and left segment 42) enclosing pillar 38, which has a top surface substantially coplanar with the upper surface of layer 22. In one embodiment, pillar 38 is formed integrally as part of layer 22. In alternative embodiments, pillar 38 may be formed from an additional insulating or conducting layer.

Abstract: A method and apparatus for removing particulate contaminants from a semiconductor wafer are disclosed. A wafer 10 is held in a wafer holder 12 at cleaning station 14. Cleaning station 14 has a rinse fluid supply system 18 which supplies, e.g. deionized water, to the wafer surface during particle removal. A cleaning pad 20 is mounted on a platen 22, substantially in the plane of wafer 10. Platen 22 is coupled to a drive mechanism 24, which may for example be an electric motor, and drive mechanism 24 is coupled to station 14 by an engagement mechanism 26 which provides vertical displacement to engage pad 20 and wafer 10 for particle removal, and also provides a controlled pad contact pressure during particle removal. In operation, rinse fluid from 18 is supplied to slowly rotating wafer 10, while pad 20 is rotated, preferably at 200 to 600 rpm, and contacted with wafer 10.

Abstract: A semiconductor device and process for making the same are disclosed which uses a dielectric stack to improve fabrication throughput, gap-fill, planarity, and within-wafer uniformity. A gap-fill dielectric layer 34 (which preferably contains an integral seed layer) is first deposited over conductors 22, 24, and 26. Layer 34 is preferably a high density plasma (HDP) silicon dioxide deposition which planarizes high aspect ratio conductors such as 24, 26 but does not necessarily planarize low aspect ratio conductors such as 22. A dielectric polish layer 40, which preferably polishes faster than the gap-fill layer may be deposited over layer 34. The polish layer may be formed, for example, by plasma chemical vapor deposition of TEOS. Finally, a chemical-mechanical polishing process is used to planarize the dielectric stack in a manner which requires a minimal polishing time and produces a highly planarized structure.