Patents by Inventor Manoj Mehrotra

Manoj Mehrotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250142800
    Abstract: Described examples include a semiconductor device having a first p-channel field effect transistor (p-FET). The first p-FET includes: a first gate dielectric layer on a surface of a substrate; a first gate structure on the first gate dielectric layer; and first silicon-germanium (SiGe) regions disposed in the substrate, on both sides of the first gate structure, the first SiGe regions extended to a first depth from the surface of the substrate. The semiconductor device also has a second p-FET. The second p-FET includes a second gate dielectric layer on the surface of the substrate; a second gate structure on the second gate dielectric layer; and second SiGe regions disposed in the substrate, on both sides of the second gate structure, the second SiGe regions extended to a second depth from the surface of the substrate, the second depth different than the first depth.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 1, 2025
    Inventor: Manoj Mehrotra
  • Patent number: 12272739
    Abstract: In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: April 8, 2025
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra
  • Publication number: 20250081558
    Abstract: The present disclosure generally relates to a semiconductor device having a reduced height gate electrode layer. In an example, a semiconductor device includes a substrate, a gate dielectric layer, a gate electrode layer, a doped source/drain region, and a dielectric layer. The gate dielectric layer is on a surface of the substrate. The gate electrode layer is on the gate dielectric layer. The doped source/drain region is in the substrate and has a metallurgical junction parallel to a plane coplanar with the surface of the substrate. The metallurgical junction extends to a first vertical distance from the surface of the substrate. The gate electrode layer has a top surface that is a second vertical distance away from the surface of the substrate. The second vertical distance is equal to or less than half of the first vertical distance. The dielectric layer is over the substrate and the gate electrode layer.
    Type: Application
    Filed: August 30, 2023
    Publication date: March 6, 2025
    Inventor: Manoj Mehrotra
  • Publication number: 20250006804
    Abstract: A semiconductor device including a contact plug formed in a contact hole using a multi-stage contact etch process. The semiconductor device comprises a source/drain region over a semiconductor substrate, an oxide layer extension extending from the source/drain region toward a gate dielectric layer, and a contact plug extending through a dielectric layer over the source/drain region, the contact plug extending through a first etch stop layer and a second etch stop layer to a horizontal remaining portion of the oxide layer extension.
    Type: Application
    Filed: June 29, 2023
    Publication date: January 2, 2025
    Inventors: Manoj Mehrotra, Yu-Lun Lin
  • Publication number: 20240363434
    Abstract: Transistors with raised source/drain structures and methods of making the transistors are described. A method for making such transistors includes forming a first gate and a second gate on a substrate, forming a p-doped region adjacent the first gate, and forming an n-doped region adjacent the second gate. The method further includes forming a silicon germanium (SiGe) region in a portion of the p-doped region. Subsequently, the method simultaneously forms raised source-drain structures over the SiGe region and on the n-doped region.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventor: Manoj Mehrotra
  • Publication number: 20230119046
    Abstract: A method includes forming first and second trenches in a semiconductor substrate. The method further includes filling the first and second trenches with polysilicon. The polysilicon is oppositely doped from the semiconductor substrate. A Schottky contact is formed on the semiconductor substrate between the first and second trenches. The method also includes forming an anode for the Schottky contact. The anode is coupled to the polysilicon in the first and second trenches.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventor: Manoj MEHROTRA
  • Patent number: 11532758
    Abstract: A method includes forming first and second trenches in a semiconductor substrate. The method further includes filling the first and second trenches with polysilicon. The polysilicon is oppositely doped from the semiconductor substrate. A Schottky contact is formed on the semiconductor substrate between the first and second trenches. The method also includes forming an anode for the Schottky contact. The anode is coupled to the polysilicon in the first and second trenches.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: December 20, 2022
    Assignee: Texas Instruments Incorporated
    Inventor: Manoj Mehrotra
  • Patent number: 11417646
    Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: August 16, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Terry J. Bordelon, Deborah J. Riley
  • Publication number: 20220199828
    Abstract: In a described example, an integrated circuit includes a substrate of a semiconductor material, a source region, a gate region, a drain region and a fin structure formed on the substrate. The fin structure includes the gate region, the source region and a drift region between the gate region and the drain region. A doped control layer is formed along at least one sidewall of the fin structure over the drift region.
    Type: Application
    Filed: December 21, 2020
    Publication date: June 23, 2022
    Inventor: MANOJ MEHROTRA
  • Publication number: 20220157972
    Abstract: In some implementations, a method includes forming first and second fins on a semiconductor substrate. The method further includes diffusing first and second implants into the semiconductor substrate and first and second fins. The method also includes patterning a field plate on the semiconductor substrate. An active device, such as a laterally-diffused metal-oxide semiconductor field effect (LDMOS) transistor can be formed in this way.
    Type: Application
    Filed: November 16, 2020
    Publication date: May 19, 2022
    Inventor: Manoj MEHROTRA
  • Publication number: 20210225711
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Application
    Filed: March 16, 2021
    Publication date: July 22, 2021
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10978353
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: April 13, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Publication number: 20210091237
    Abstract: A method includes forming first and second trenches in a semiconductor substrate. The method further includes filling the first and second trenches with polysilicon. The polysilicon is oppositely doped from the semiconductor substrate. A Schottky contact is formed on the semiconductor substrate between the first and second trenches. The method also includes forming an anode for the Schottky contact. The anode is coupled to the polysilicon in the first and second trenches.
    Type: Application
    Filed: September 24, 2019
    Publication date: March 25, 2021
    Inventor: Manoj MEHROTRA
  • Publication number: 20190103321
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10163725
    Abstract: An integrated circuit containing an n-channel finFET and a p-channel finFET is formed by forming a first polarity fin epitaxial layer for a first polarity finFET, and subsequently forming a hard mask which exposes an area for a second, opposite, polarity fin epitaxial layer for a second polarity finFET. The second polarity fin epitaxial layer is formed in the area exposed by the hard mask. A fin mask defines the first polarity fin and second polarity fin areas, and a subsequent fin etch forms the respective fins. A layer of isolation dielectric material is formed over the substrate and fins. The layer of isolation dielectric material is planarized down to the fins. The layer of isolation dielectric material is recessed so that the fins extend at least 10 nanometers above the layer of isolation dielectric material. Gate dielectric layers and gates are formed over the fins.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: December 25, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Manoj Mehrotra, Charles Frank Machala, III, Rick L. Wise, Hiroaki Niimi
  • Patent number: 10103714
    Abstract: Apparatuses and methods to adjust voltage for thermal mitigation are provided. The apparatus includes a circuit, a plurality of switches configured to provide power of a power domain to the circuit, a plurality of thermal sensors disposed at different locations about the circuit and configured to detect temperatures at the different locations, and a control circuit configured to determine that one of the detected temperatures at one of the locations exceeds a temperature threshold, and in response, adjust one or more of the plurality of switches in proximity with the one location to reduce power provided to the circuit. The method includes providing power of a power domain through a plurality of switches, detecting a temperature at a location exceeding a temperature threshold, and adjusting the plurality of switches in proximity with the location to reduce the power provided, in response to the detecting the temperature exceeding the temperature threshold.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: October 16, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Manoj Mehrotra, Yuancheng Chris Pan, Shih-Hsin Jason Hu
  • Patent number: 10042405
    Abstract: Apparatuses and methods to adjust a source voltage based on stored information are provided. The apparatus includes a circuit configured to receive power from a power source through a power distribution network, a storage medium storing data specifying one or more electrical characteristics of the circuit, and a control circuit configured to adjust a source voltage at the power source based on the data stored in the storage medium. The method includes receiving power by a circuit from a power source through a power distribution network, reading data specifying one or more electrical characteristics of the circuit from a storage medium, and adjusting a source voltage at the power source based on the data stored in the storage medium.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Manoj Mehrotra
  • Patent number: 10026839
    Abstract: A process of forming an integrated circuit containing a first transistor and a second transistor of the same polarity, by forming an epitaxial spacer layer over gates of both transistors, performing an epitaxial spacer anisotropic etch process to form epitaxial spacers on vertical surfaces adjacent to the first transistor gate and removing the epitaxial spacer layer from the second transistor gate, subsequently performing a source/drain etch process and a source/drain epitaxial process to form source/drain epitaxial regions in the substrate adjacent to the first and second gates, such that the first source/drain epitaxial regions are separated from the first gate by a lateral space which is at least 2 nanometers larger than a second lateral space separating the second source/drain epitaxial regions from the second gate. An integrated circuit formed by the recited process.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: July 17, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Manoj Mehrotra
  • Patent number: 9960162
    Abstract: An integrated circuit and method with a metal gate NMOS transistor with a high-k first gate dielectric on a high quality thermally grown interface dielectric and with a metal gate PMOS transistor with a high-k last gate dielectric on a chemically grown interface dielectric.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: May 1, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Hiroaki Niimi, Manoj Mehrotra, Mahalingam Nandakumar
  • Patent number: 9915968
    Abstract: The present disclosure is directed to mitigating voltage droops. An aspect includes outputting, by a clock module coupled to a multiplexor, a first clock signal to the multiplexor, the first clock signal generated by a clock delay component of the clock module, receiving, by the clock module, a second clock signal from a phase-locked loop (PLL), wherein the PLL outputs a third clock signal to a processor coupled to the PLL and the multiplexor, selecting, by the multiplexor, the first clock signal to output to the processor based on detecting a droop in voltage on a power supply, and selecting, by the multiplexor, the third clock signal to output to the processor based on detecting that the droop in the voltage on the power supply has passed, wherein the clock module and the processor are coupled to the power supply.
    Type: Grant
    Filed: April 19, 2016
    Date of Patent: March 13, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Virendra Bansal, Manoj Mehrotra, Keith Alan Bowman