Patents by Inventor Manoj Mehta
Manoj Mehta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11301619Abstract: A system and a method for transforming a contract into a digital contract for deployment over a decentralized platform. The system uses blockchain and artificial intelligence to automatically execute contracts. The system is configured to capture the intent, milestones and events of a contract in smart contract codes. In order to achieve this without any imposing transition costs on users, natural language processing is utilized to draft contract and the system generates the same contract in a pre-defined standardized form. The contract in standardized form is converted to respective parse tree and abstract syntax tree. The abstract syntax tree is converted to digital contract. The digital contract is compiled and deployed on to a blockchain network.Type: GrantFiled: March 15, 2021Date of Patent: April 12, 2022Assignee: ZENSAR TECHNOLOGIES LIMITEDInventors: Sudeep Choudhari, Pvs Chanakya Yadav, Prem Manoj Mehta, Aditi Yaduvanshi, Shreshtha Mitra
-
Publication number: 20210286936Abstract: A system and a method for transforming a contract into a digital contract for deployment over a decentralized platform. The system uses blockchain and artificial intelligence to automatically execute contracts. The system is configured to capture the intent, milestones and events of a contract in smart contract codes. In order to achieve this without any imposing transition costs on users, natural language processing is utilized to draft contract and the system generates the same contract in a pre-defined standardized form. The contract in standardized form is converted to respective parse tree and abstract syntax tree. The abstract syntax tree is converted to digital contract. The digital contract is compiled and deployed on to a blockchain network.Type: ApplicationFiled: March 15, 2021Publication date: September 16, 2021Inventors: Sudeep Choudhari, PVS Chanakya Yadav, Prem Manoj Mehta, Aditi Yaduvanshi, Shreshtha Mitra
-
Publication number: 20170257304Abstract: A prognostics module includes a systems analysis module and a determination module. The systems analysis module is configured to obtain operational information corresponding to a system-wide operation of a multi-element system. The multi-element system includes multiple elements communicatively coupled by at least one common communication link. The determination module is configured to determine a future health of at least one of the multiple elements of the multi-element system using the operational information corresponding to the system-wide operation of the multi-element system.Type: ApplicationFiled: March 7, 2016Publication date: September 7, 2017Inventors: Mohak Shah, Scott Charles Evans, Budhaditya Deb, Anthony Gerard Gargulak, Thomas Lasky, Manoj Mehta
-
Patent number: 9282008Abstract: A prognostics module includes a systems analysis module and a determination module. The systems analysis module is configured to obtain operational information corresponding to a system-wide operation of a multi-element system. The multi-element system includes multiple elements communicatively coupled by at least one common communication link. The determination module is configured to determine a future health of at least one of the multiple elements of the multi-element system using the operational information corresponding to the system-wide operation of the multi-element system.Type: GrantFiled: June 11, 2013Date of Patent: March 8, 2016Assignee: GENERAL ELECTRIC COMPANYInventors: Mohak Shah, Scott Charles Evans, Budhaditya Deb, Anthony Gerard Gargulak, Thomas Lasky, Manoj Mehta
-
Publication number: 20140365638Abstract: A prognostics module includes a systems analysis module and a determination module. The systems analysis module is configured to obtain operational information corresponding to a system-wide operation of a multi-element system. The multi-element system includes multiple elements communicatively coupled by at least one common communication link. The determination module is configured to determine a future health of at least one of the multiple elements of the multi-element system using the operational information corresponding to the system-wide operation of the multi-element system.Type: ApplicationFiled: June 11, 2013Publication date: December 11, 2014Inventors: Mohak Shah, Scott Charles Evans, Budhaditya Deb, Anthony Gerard Gargulak, Thomas Lasky, Manoj Mehta
-
Patent number: 7502977Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: January 21, 2005Date of Patent: March 10, 2009Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
-
Patent number: 7490260Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: September 1, 2005Date of Patent: February 10, 2009Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
-
Patent number: 7318115Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: GrantFiled: August 27, 2003Date of Patent: January 8, 2008Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
-
Patent number: 7287148Abstract: An integrated circuit comprising a reduced instruction set computer (RISC) controller to execute RISC instructions, one or more digital signal processing (DSP) units to execute DSP instructions, and a unified instruction pipeline coupled to the RISC controller and the one or more DSP units, the unified instruction pipeline to decode and initiate execution of the RISC instructions and the DSP instructions of a unified RISC and DSP instruction set, the unified instruction pipeline to decode and initiate the RISC instructions when the DSP instructions are inactive, and to decode and initiate the DSP instructions when the RISC instructions are inactive.Type: GrantFiled: August 28, 2003Date of Patent: October 23, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
-
Patent number: 7233166Abstract: Bus state keepers to maintain a steady state of an inactive bus to conserve power. In one embodiment of the invention, the bus state keepers include a plurality of multiplexers and a plurality of flip flops. The plurality of flip flops to store a state of a bus in response to a select signal.Type: GrantFiled: August 27, 2003Date of Patent: June 19, 2007Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
-
Patent number: 7111190Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: GrantFiled: January 24, 2002Date of Patent: September 19, 2006Assignee: Intel CorporationInventors: Siva Venkatraman, Earle F. Philhower, III, Ruban Kanapathippillai, Manoj Mehta
-
Publication number: 20060010335Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: ApplicationFiled: September 1, 2005Publication date: January 12, 2006Inventors: Siva Venkatraman, Earle Philhower, Ruban Kanapathippillai, Manoj Mehta
-
Patent number: 6928076Abstract: One aspect of the invention relates to a messaging communication scheme for controlling, configuring, monitoring and communicating with a signal processor within a Voice Over Packet (VoP) subsystem without knowledge of the specific architecture of the signal processor. The messaging communication scheme may feature the transmission of control messages between a signal processor and a host processor. Each control message comprises a message header portion and a control header portion. The control header portion includes at least a catalog parameter that indicates a selected grouping of control messages and a code parameter that indicates a selected operation of the selected grouping.Type: GrantFiled: September 21, 2001Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Manoj Mehta, Saurin Shah, Dianne Steiger, Chris Lawton, Anurag Bist
-
Publication number: 20050146910Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.Type: ApplicationFiled: January 21, 2005Publication date: July 7, 2005Inventors: Siva Venkatraman, Earle Philhower, Ruban Kanapathippillai, Manoj Mehta
-
Publication number: 20050076194Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 28, 2003Publication date: April 7, 2005Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle Philhower, Manoj Mehta, Kenneth Malich
-
Publication number: 20040236896Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 27, 2003Publication date: November 25, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
-
Patent number: 6732203Abstract: In one embodiment, a bus multiplexer is between a memory and a functional unit of the integrated circuit. An input of the bus multiplexer couples to a global bus having a bit width. A local bus having a lesser bit width couples to an output of the bus multiplexer. The bus multiplexer selectively multiplexes bits of data on the global bus onto bits of the local bus. In another embodiment, an integrated circuit comprises a memory, a global bus, and a functional unit coupled together. The functional unit includes a bus multiplexer with an input coupled to the global bus, and a local bus coupled to an output of the bus multiplexer. The bus width of the local bus is less than that of the global bus. The bus multiplexer selects data from a subset of bits of the global bus to couple onto the bits of the local bus.Type: GrantFiled: March 29, 2002Date of Patent: May 4, 2004Assignee: Intel CorporationInventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, III, Manoj Mehta, Kenneth Malich
-
Publication number: 20040078612Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 21, 2003Publication date: April 22, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
-
Publication number: 20040078608Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 29, 2003Publication date: April 22, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich
-
Publication number: 20040039952Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.Type: ApplicationFiled: August 27, 2003Publication date: February 26, 2004Inventors: Ruban Kanapathippillai, Kumar Ganapathy, Thu Nguyen, Siva Venkatraman, Earle F. Philhower, Manoj Mehta, Kenneth Malich