Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Abstract: Method and apparatus for reducing power consumption in a digital specific signal processor integrated circuit. Data buses are routed through multiplexers to reduce the number of busses routed across an integrated circuit and maintain their prior state. Global memory is clustered into memory clusters. The memory cluster having a memory block to be accessed is activated without activating other memory clusters in the global memory. Inactive data buses retain their state by use of bus state keepers. A loop buffer stores instructions within program loops to avoid memory accesses. Functional blocks can have their clocks gated instruction by instruction to lower power consumption. RISC and DSP units swap circuit activity to reduce power consumption. Local data memory is includes self-timed memory access activation and provides for off boundary access to further lower power consumption.

Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Abstract: A reconfigurable memory in an integrated circuit includes an array of memory cells and a memory controller. The array of memory cells in the reconfigurable memory are tested to determine if they are unusable and if so, their associated physical addresses corresponding to their physical location. After determining the physical addresses where any failure exists, the physical addresses locations associated with the physical locations of unusable memory cells or memory blocks are mapped out to avoid addressing them. While mapping out unusable memory locations or memory blocks reduces the total capacity, the reconfigurable memory has sufficient capacity for the integrated circuit to remain functionally usable.

Abstract: One aspect of the invention relates to a messaging communication scheme for controlling, configuring, monitoring and communicating with a signal processor within a Voice Over Packet (VoP) subsystem without knowledge of the specific architecture of the signal processor. The messaging communication scheme may feature the transmission of control messages between a signal processor and a host processor. Each control message comprises a message header portion and a control header portion. The control header portion includes at least a catalog parameter that indicates a selected grouping of control messages and a code parameter that indicates a selected operation of the selected grouping.

Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.

Abstract: A system for synchronizing the upstream burst transmission in a cable system to a time specified by the cable head end is disclosed. The system includes a free running counter within a cable modem (CM) or network interface unit (NIU), along with logic to capture the value of this free running counter at the time a frame of MPEG-2 SYNC data arrives, to create a time tag stored in memory. A computer within the cable modem or network interface unit has access to the time tags in memory and the contents of a time synchronization message from the head end, also stored in memory. The computer contains a program to calculate the value of the local counter that corresponds to a time to transmit commanded by the cable system head end. The system includes logic within the CM or NIU to initiate an upstream burst transmission when the value of the local counter becomes equal to a calculated value, thus causing the cable modem to initiate its upstream burst transmission precisely at the time commanded by the head end.