Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

Abstract: Systems, apparatuses, and methods for enabling indirect chaining of command buffers are disclosed. A system includes at least first and second processors and a memory. The first processor generates a plurality of command buffers and stores the plurality of command buffers in the memory. The first processor also generates and stores, in the memory, a table with entries specifying addresses of the plurality of command buffers and an order in which to process the command buffers. The first processor conveys an indirect buffer packet to the second processor, where the indirect buffer packet specifies a location and a size of the table in the memory. The second processor retrieves an initial entry from the table, processes a first command buffer at the address specified in the initial entry, and then returns to the table for the next entry upon completing processing of the first command buffer.

Abstract: A system includes a processing unit such as a GPU that itself includes a command processor configured to receive instructions for execution from a software application. A processor pipeline coupled to the processing unit includes a set of parallel processing units for executing the instructions in sets. A set manager is coupled to one or more of the processor pipeline and the command processor. The set manager includes at least one table for storing a set start time, a set end time, and a set execution time. The set manager determines an execution time for one or more sets of instructions of a first window of sets of instructions submitted to the processor pipeline. Based on the execution time of the one or more sets of instructions, a set limit is determined and applied to one or more sets of instructions of a second window subsequent to the first window.

Abstract: An apparatus may identify each object of a set of objects included in a first location, wherein the set of objects includes at least one IoT device and at least one other object. The apparatus may determine a first set of attributes for the at least one IoT device. The apparatus may store registration information associated with the at least one IoT device, the registration information including a first identifier associated with the at least one IoT device and including the first set of attributes for the at least one IoT device. The apparatus may obtain an input. The apparatus may determine whether the input corresponds to the at least one IoT device based on the registration information associated with the at least one IoT device. The apparatus may control the at least one IoT device when the input corresponds to the at least one IoT device.

Abstract: An integrated circuit is configured to compute multiply-accumulate (MAC) operations in convolutional neural networks. The integrated circuit includes a lookup table (LUT) configured to store multiple values. The integrated circuit also includes a compute unit. The compute unit is composed of an accumulator. The compute unit also includes a first multiplier configured to receive a first value of a padded input feature and a first weight of a filter kernel. The compute unit also includes a first selector. The first selector is configured to select an input to supply to the accumulator between an output from the first multiplier and an output from the LUT.

Abstract: An apparatus for optimizing a computational network is configure to receive an input at a first processing component. The first processing component may include at least a first programmable processing component and a second programmable processing component. The first programmable processing component is configured to compute a first nonlinear function and the second programmable processing component is configured to compute a second nonlinear function which is different than the second nonlinear function. The computational network which may be a recurrent neural network such as a long short-term memory may be operated to generate an inference based at least in part on outputs of the first programmable processing component and the second programmable processing component.

Abstract: An apparatus for operating a computational network, such as a long short term memory, is configured to compute in a first cell, an input for a cell of a next layer based on a prior hidden state and a current input. A memory state may be computed for the first cell based on a prior memory state, the prior hidden state, and the current input. The first cell outputs the computed input to the next layer cell, which may also receive a second prior memory state, a second prior hidden state. In turn, the next layer cell computes an input for a subsequent layer cell based on the second prior hidden state and the input supplied by the first cell in parallel with the first cell computing a hidden state and a memory state to be supplied to a subsequent cell in the same layer.

Abstract: A method of interfacing an event based processing system with a frame based processing system is presented. The method includes converting multiple events into a frame. The events may be generated from an event sensor. The method also includes inputting the frame into the frame based processing system.

Abstract: A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling.

Abstract: A method for computing a spatial Fourier transform for an event-based system includes receiving an asynchronous event output stream including one or more events from a sensor. The method further includes computing a discrete Fourier transform (DFT) matrix based on dimensions of the sensor. The method also includes computing an output based on the DFT matrix and applying the output to an event processor.

Abstract: A particular apparatus includes a magnetic tunnel junction (MTJ) device and a transistor. The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition points that correspond to magnetic switching points of the MTJ device.

Abstract: A particular apparatus includes a magnetic tunnel junction (MTJ) device and a transistor. The MTJ device and the transistor are included in a comparator that has a hysteresis property associated with multiple transition points that correspond to magnetic switching points of the MTJ device.

Abstract: A method of event-based down sampling includes receiving multiple sensor events corresponding to addresses and time stamps. The method further includes spatially down sampling the addresses based on the time stamps and the addresses. The method may also include updating a pixel value for each of the multiple sensor events based on the down sampling.

Abstract: A method for computing a spatial Fourier transform for an event-based system includes receiving an asynchronous event output stream including one or more events from a sensor. The method further includes computing a discrete Fourier transform (DFT) matrix based on dimensions of the sensor. The method also includes computing an output based on the DFT matrix and applying the output to an event processor.

Abstract: A method of interfacing an event based processing system with a frame based processing system is presented. The method includes converting multiple events into a frame. The events may be generated from an event sensor. The method also includes inputting the frame into the frame based processing system.

Abstract: A method of processing asynchronous event-driven input samples of a continuous time signal, includes calculating a convolutional output directly from the event-driven input samples. The convolutional output is based on an asynchronous pulse modulated (APM) encoding pulse. The method further includes interpolating output between events.