Abstract: Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a photodiode and a floating diffusion region. The floating diffusion region may be coupled to a charge storage structure for a low conversion gain configuration and can be coupled to a charge storage structure for a medium conversion gain configuration. The medium conversion gain charge storage structure may be activated when transferring photodiode charge to the floating diffusion region for a high conversion gain configuration. The control circuitry may control each pixel to perform a high conversion gain readout operation, a medium conversion gain readout operation, and a low conversion gain readout operation. If desired, the medium conversion gain readout operation may be omitted.

Abstract: Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to row control circuitry and column readout circuitry. An image pixel in the array may include a charge integration portion having a photodiode, a floating diffusion region, and a capacitor coupled to the floating diffusion region and may include a voltage-domain sampling portion having three capacitors. High light and low light image level and reset level signals may be sampled and stored at the voltage-domain sampling portion before being readout to the column readout circuitry during a readout operation. The high light reset level signal may be sampled and stored during the readout operation.

Abstract: A passive amplifier is provided that includes an input sampling switch, a sampling capacitance, and metal-oxide-semiconductor capacitor devices. An input signal may be sampled onto the sampling capacitance by turning on the input sampling switch while the metal-oxide-semiconductor capacitors are activated. After the sampling phase, the metal-oxide-semiconductor capacitors are deactivated to provide a voltage gain. The voltage gain can be conditionally applied depending on the signal level of the sampled input.

Abstract: Some image sensors include pixels with capacitors. The capacitor may be used to store charge in the imaging pixel before readout. The capacitor may be a metal-insulator-metal (MIM) capacitor that is susceptible to dielectric relaxation. Dielectric relaxation may cause lag in the signal on the capacitor that impacts the signal on the capacitor during sampling. The image sensor may include dielectric relaxation correction circuitry that leverages the linear relationship between voltage stress and lag signal to correct for dielectric relaxation. The image sensor may include shielded pixels that operate with a similar timing scheme as the imaging pixels in the active array. Measured lag signals from the shielded pixels may be used to correct imaging data.

Abstract: An image sensor may include an array of image pixels. The array of image pixel may be coupled to control circuitry and readout circuitry. One or more image pixels in the array may each include a coupled-gates structure coupling a photodiode at one input terminal to a capacitor at a first output terminal and to a floating diffusion region at a second output terminal. The coupled-gates structure may include a first transistor that sets a potential barrier defining overflow portions of the photodiode-generated charge. Second and third transistors in the coupled-gates structure may be modulated to transfer the overflow charge to the capacitor and to the floating diffusion region at suitable times. The second and third transistors may form a conductive path between the capacitor and the floating diffusion region for a low conversion gain mode of operation.

Abstract: Implementations of a semiconductor device may include a photodiode included in a second epitaxial layer of a semiconductor substrate; light shield coupled over the photodiode; and a first epitaxial layer located in one or more openings in the light shield. The first epitaxial layer and the second epitaxial layer may form a single crystal.

Abstract: An image sensor may include an analog-to-digital converter. The converter may have a input capacitor, one or more metal-oxide-semiconductor capacitors, a digital-to-analog converter, and a comparator. An input signal may be sampled onto the input capacitor while the metal-oxide-semiconductor capacitors are activated. A few conversion steps may be performed while the metal-oxide-semiconductor capacitors are activated. After the few conversion steps, the metal-oxide-semiconductor capacitors are deactivated to realize a voltage gain, which makes the converter less sensitive to comparator noise.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: An imaging system may include an array of image sensor pixels, each image sensor pixel including a photosensitive element coupled to time trace generation circuitry having a first CCD register. The time trace generation circuitry may be coupled to integration circuitry having a second integration CCD register via corresponding charge transfer structures. The second integration CCD register may integrate multiples sets of sampled charge from the first CCD register to improve the signal-to-noise ratio of the collected time trace information. The time trace generations circuitry or integration circuitry may also include background light subtract capabilities to remove background light level from the collected time trace information.

Abstract: An imaging system may include an array of image pixels, each image pixel including two photodiodes. A first photodiode may surround a second photodiode. Each image pixel may include two low gain capacitors. A first low gain capacitor may be coupled to a floating diffusion region connected to the two photodiodes via respective transistors. A second low gain capacitor may be coupled to the second photodiode directly or via an interposing transistor. Charge generated by the first photodiode may be separated into an overflow portion stored at the first low gain capacitor and a remaining portion stored at the first photodiode. The overflow charge portion may be used to generated a first signal. The remaining charge portion (along with other charge generated by the first photodiode) may be used to generate a second signal. The charge generated by the second photodiode may be used to generated a third signal.

Abstract: An imaging system may include an image sensor having an image sensor. The image sensor may include an image sensor pixel array coupled to row control circuitry and column readout circuitry. The image sensor pixel array may include a plurality of image sensor pixels. Each image sensor pixel may include a photosensitive element configured to generate charge in response to incident light, a first charge storage structure configured to accumulate an overflow portion of the generated charge for a low gain signal and a second charge storage structure configured to store a remaining portion of the generated charge for a high gain signal. Each image sensor pixel may also include a dedicated overflow charge storage structure interposed between the first charge storage structure and a floating diffusion region.

Abstract: Implementations of pixels may include a photodiode layer including a photodetector and two or more silicon based circular transistors and an interconnect layer coupled to the photodiode layer. The interconnect layer may include an amorphous oxide semiconductor (AOS) transistor operatively coupled with the two or more silicon based circular transistors.

Abstract: Image sensors may include an array of pixels each having nested sub-pixels. Nested sub-pixels may include an inner photosensitive region and an outer photosensitive region. Inner photosensitive regions of pixels in an array may be provided with a respective local vertical transfer gate structure formed in a trench that laterally surrounds the inner photosensitive region. A trench structure may be formed in a grid-like pattern having gaps in which the nested sub-pixels are formed. The trench structure may be coupled to outer photosensitive regions of each of the pixels in the array. The trench structure may be a global vertical transfer gate structure. The vertical transfer gate structures provided to the pixels may allow for accumulated charges to be transferred to respective charge storage nodes associated with the photosensitive regions in any given pixel. Image sensors formed in this way may be used in rolling shutter or global shutter configurations.

Abstract: Various embodiments of the present technology provide a method and apparatus for signal distribution in an image sensor. In various embodiments, the apparatus provides a balanced signal distribution circuit having a plurality of driver circuits, wherein each driver circuit is connected to a logic circuit, distributed either directly below the pixel array or interspersed within the pixel array. A clock distribution network is connected to the logic circuit to provide all the logic circuits with a clock signal substantially simultaneously, which, in turn, controls all of the driver circuits substantially simultaneously and all pixels in the pixel array receive a control signal substantially simultaneously.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.

Abstract: Image sensors may include multiple vertically stacked photodiodes interconnected using vertical deep trench transfer gates. A first n-epitaxial layer may be formed on a residual substrate; a first p-epitaxial layer may be formed on the first n-epitaxial layer; a second n-epitaxial layer may be formed on the first p-epitaxial layer; a second p-epitaxial layer may be formed on the second n-epitaxial layer; and so on. The n-epitaxial layers may serve as accumulation regions for the different epitaxial photodiodes. A separate color filter array is not needed. The vertical transfer gates may be a deep trench that is filled with doped conductive material, lined with gate dielectric liner, and surrounded by a p-doped region. Image sensors formed in this way may be used to support a rolling shutter configuration or a global shutter configuration and can either be front-side illuminated or backside illuminated.