Patents by Inventor Mao Chen
Mao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137795Abstract: This application relates to the field of communications technologies. A method includes: A first device receives first configuration information sent by a second device. The first configuration information includes at least one of information about a reference signal, frequency range information of a radio frequency signal, or bandwidth range information. The first device measures a first reference signal set, to obtain a first measured value. The first reference signal set includes at least two reference signals. The first device determines an expansion factor ? based on the first configuration information. The first device determines a second measured value based on the first measured value and the expansion factor ?.Type: ApplicationFiled: October 24, 2023Publication date: April 25, 2024Inventors: Mao Yan, Huang Huang, Hua Shao, Lei Chen
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Publication number: 20240131644Abstract: Disclosed is a selective field-assisted machining system. The system includes a micron-level high-speed identification module, an in-situ laser assisted module, an ultrasonic vibration module, an energy field loading high-speed control module, and a diamond tool. The micron-level high-speed identification module is used to quickly identify the type of a material substrate of a workpiece to be processed, process the identification information into a corresponding control signal, and send same to the energy field loading high-speed control module to implement selective processing of the workpiece to be processed, i.e. to process brittle particles using in-situ laser assisted machining and to process a soft metal substrate using ultrasonic vibration processing. In the present invention, ultra-precision cutting of brittle particles and a soft metal substrate can be completed at the same time in a single processing process.Type: ApplicationFiled: December 25, 2023Publication date: April 25, 2024Applicant: HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGYInventors: Jianfeng XU, Zhengding ZHENG, Jianguo ZHANG, Kai HUANG, Mao WANG, Xiao CHEN, Junfeng XIAO
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Publication number: 20240130856Abstract: A heart valve prosthesis device includes a stent and leaflets. The stent includes an annular part and guide parts. A first end of the annular part includes cell sections arranged in sequence in a circumferential direction of the annular part. The guide parts are arranged at intervals in the circumferential direction of the annular part, one side of each guide part is connected to a corresponding cell section, and the other side gradually tapers to an end where a retrieval cell is provided for a pulling wire to pass through. Each guide part includes a first region being the retrieval cell, a second region aligned with the first region and configured as a central region, and a third region and a fourth region distributed on two sides of the central region in the circumferential direction of the annular part.Type: ApplicationFiled: December 25, 2023Publication date: April 25, 2024Inventors: Quangang Gong, Mao Chen, Yuan Feng, Yaru Li, Dan Rui
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Patent number: 11961637Abstract: This disclosure relates to a stretchable composite electrode and a fabricating method thereof, and particularly relates to a stretchable composite electrode including a silver nanowire layer and a flexible polymer film and a fabricating method thereof.Type: GrantFiled: December 7, 2022Date of Patent: April 16, 2024Assignee: TPK ADVANCED SOLUTIONS INC.Inventors: Wei Sheng Chen, Ching Mao Huang, Jia Hui Zhou, Huan Ran Yu, Shu Xiong Wang, Chin Hui Lee
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Patent number: 11948914Abstract: A package structure and a method of forming the same are provided. The package structure includes a package substrate, a semiconductor chip disposed over the package substrate, and an integrated device located below and bonded to the lower surface of the semiconductor chip. The semiconductor chip has a lower surface facing the package substrate and is electrically connected to the package substrate through conductive structures. The integrated device is laterally surrounded by the conductive structures, and the integrated device and the conductive structures are located within boundaries of the semiconductor chip when viewed in a direction perpendicular to the lower surface of the semiconductor chip.Type: GrantFiled: July 20, 2022Date of Patent: April 2, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng-Cheng Hsu, Shin-Puu Jeng, Shuo-Mao Chen
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Patent number: 11938283Abstract: A bendable sheath and a delivery system using the bendable sheath. The bendable sheath comprises a tube body (3). The tube body (3) comprises a distal end and a proximal end. A tube wall of the tube body (3) is connected to a pull wire (8). One end of the pull wire (8) extends towards the proximal end of the tube body (3), and the other end is connected to the tube body (3) near the distal end of the tube body (3). The pull wire (8) comprises at least a section thereof disposed freely outside the tube body (3) and near the distal end of the tube body (3). The pull wire (8) in the bendable sheath comprises the section disposed freely outside the sheath tube body (3) and, when pulled, the section is disposed so as to facilitate the application of force. The section moves relative to the tube body (3), such that a force application point is adaptively changed.Type: GrantFiled: September 2, 2020Date of Patent: March 26, 2024Assignee: VENUS MEDTECH (HANGZHOU), INC.Inventors: Mao Chen, Yuan Feng, Zhifei Zhang, Feng Guo, Quangang Gong, Shiguang Wu
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Patent number: 11942408Abstract: A method includes: bonding a plurality of interposer dies to a first redistribution layer (RDL), each of the interposer dies comprising a substrate and a second RDL below the substrate; encapsulating the first RDL and the interposer dies; reducing a thickness of the substrate of each of the interposer dies; and electrically coupling the interposer dies to a first semiconductor die.Type: GrantFiled: May 20, 2022Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shuo-Mao Chen, Feng-Cheng Hsu, Shin-Puu Jeng
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Patent number: 11935837Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.Type: GrantFiled: March 30, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Feng Wei Kuo, Chewn-Pu Jou, Shuo-Mao Chen
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Patent number: 11934027Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.Type: GrantFiled: June 21, 2022Date of Patent: March 19, 2024Assignee: TDK TAIWAN CORP.Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
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Patent number: 11937405Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.Type: GrantFiled: July 28, 2021Date of Patent: March 19, 2024Assignee: QUANTA COMPUTER INC.Inventors: Chao-Jung Chen, Yu Nien Huang, Sin-Hong Lien, Jen-Mao Chen
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Publication number: 20240087903Abstract: Provided is a package structure including a die, a through via, an encapsulant, a warpage controlling layer, and a cap. The through via is laterally aside the die. The encapsulant laterally encapsulates the through via and the die. The warpage controlling layer covers the encapsulant and the die. The cap is laterally aside the warpage controlling layer and on the through via. The cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the warpage controlling layer.Type: ApplicationFiled: November 16, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
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Publication number: 20240088124Abstract: A semiconductor structure, comprising a redistribution layer (RDL) including a dielectric layer and a conductive trace within the dielectric layer; a first conductive member disposed over the RDL and electrically connected with the conductive trace; a second conductive member disposed over the RDL and electrically connected with the conductive trace; a first die disposed over the RDL; a second die disposed over the first die, the first conductive member and the second conductive member; and a connector disposed between the second die and the second conductive member to electrically connect the second die with the conductive trace, wherein the first conductive member is electrically isolated from the second die.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: HSIANG-TAI LU, SHUO-MAO CHEN, MILL-JER WANG, FENG-CHENG HSU, CHAO-HSIANG YANG, SHIN-PUU JENG, CHENG-YI HONG, CHIH-HSIEN LIN, DAI-JANG CHEN, CHEN-HUA LIN
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Patent number: 11911991Abstract: An apparatus and method for expanding a box blank into a box, the apparatus comprising an arm assembly, a controller, a camera and a box blank conveyor. The arm assembly includes a folding arm having a position in a first direction and a rotational angle controlled by the controller based on a position of a feature of the box blank in the field of view of the camera. The camera captures images of the box blank which are used to position the arm assembly and to evaluate the need to reject a box blank.Type: GrantFiled: July 21, 2022Date of Patent: February 27, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Szu-Chen Huang, Fu-Hsien Li, Mao-Jung Chiu, Mao-Shun Lien, Po-Hsien Chiu
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Patent number: 11915992Abstract: A method for forming a package structure is provided, including forming an interconnect structure over a carrier substrate and forming a semiconductor die over a first side of the interconnect structure. A removable film is formed over the semiconductor die. The method includes forming a first stacked die package structure over the first side of the interconnect structure. A top surface of the removable film is higher than a top surface of the first stacked die package structure. The method includes forming a package layer, removing a portion of the package layer to expose a portion of the removable film, removing the removable film to form a recess, forming a lid structure over the semiconductor die and the first stacked die package structure. The lid structure has a main portion and a protruding portion disposed in the recess and extending from the main portion.Type: GrantFiled: February 24, 2022Date of Patent: February 27, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shin-Puu Jeng, Po-Yao Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Chin-Hua Wang
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Publication number: 20240063182Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.Type: ApplicationFiled: November 3, 2023Publication date: February 22, 2024Inventors: Shin-Puu Jeng, Po-Yao Chuang, Shuo-Mao Chen
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Patent number: 11908764Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.Type: GrantFiled: August 31, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Liang Lin, Po-Yao Chuang, Te-Chi Wong, Shuo-Mao Chen, Shin-Puu Jeng
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Patent number: 11910563Abstract: A computing device comprises a housing, a heat-generating electronic component, at least one additional electronic component, and a liquid cooling module. The heat-generating component, the at least one additional electronic component, and the liquid cooling module are all positioned inside the housing. The liquid cooling module is configured to cool the heat-generating electronic component, and includes at least one movable radiator. The at least one movable radiator is configured to move between a first position and a second position. When the at least one movable radiator is in the first position, the at least one movable radiator blocks access to the at least one additional electronic component within the housing. When the at least one movable radiator is in the second position, the at least one movable radiator allows access to the at least one additional electronic component within the housing.Type: GrantFiled: June 21, 2021Date of Patent: February 20, 2024Assignee: QUANTA COMPUTER INC.Inventors: Jen-Mao Chen, Wei-En Tsai, Sin-Hong Lien, Jhih-Bin Guan
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Publication number: 20240053805Abstract: A method and system controls cooling system leaks in a rack. The method includes monitoring leak detection sensors positioned at computer systems and below sections of a liquid conveyance system. In response to determining if a signal was received from one of the leak detection sensors that is indicative of a leak, the leak detection sensor and the corresponding one of the plurality of computer systems associated the received signal is determined. Power is disconnected to the corresponding one of the computer systems and a signal is transmitted to implement moving first and second valves from open to closed positions. The first valve is positioned within the liquid conveyance system between a hot rack manifold and a thermal contact structure associated with the computer system associated with the received signal. The second valve is positioned within the liquid conveyance system between a cool rack manifold and the thermal contact structure.Type: ApplicationFiled: October 27, 2023Publication date: February 15, 2024Inventors: Chao-Jung Chen, Yu-Nien Huang, Sin-Hong Lien, Jen-Mao Chen
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Patent number: 11894279Abstract: Present disclosure provides a semiconductor stress monitoring structure, including a substrate, first conductive segments over the substrate, second conductive segments and a sensing structure proximate to the substrate. The first conductive segments are arranged parallel to each other. The second conductive segments are arranged below the first conductive segments and parallel to each other. The first conductive segments and the second conductive segments extend in the same direction. The sensing structure is configured to respond to a stress caused by the first conductive segments and the second conductive segments and generate a monitoring signal.Type: GrantFiled: July 29, 2022Date of Patent: February 6, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chien-Mao Chen
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Patent number: 11887952Abstract: A package structure includes a first dielectric layer, a first semiconductor device over the first dielectric layer, a first redistribution line in the first dielectric layer, a second dielectric layer over the first semiconductor device, a second semiconductor device over the second dielectric layer, a second redistribution line in the second dielectric layer, a conductive through-via over the first dielectric layer and electrically connected to the first redistribution line, a conductive ball over the conductive through-via and electrically connected to the second redistribution line, and a molding material. The molding material surrounds the first semiconductor device, the conductive through-via, and the conductive ball, wherein a top of the conductive ball is higher than a top of the molding material.Type: GrantFiled: July 27, 2022Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Puu Jeng, Shuo-Mao Chen, Feng-Cheng Hsu