Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures surrounded by the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features, and the reinforced plate is thinner than the redistribution structure. A thickness ratio of a first thickness of the reinforced plate to a second thickness of the redistribution structure is greater than about 0.5. The package structure further includes one or more chip structures bonded to the redistribution structure.

Abstract: An integrated circuit package integrates a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the oDie and/or the eDie, where molded material at least partially surrounds the at least one of the oDie and/or the eDie.

Abstract: A method of verifying an integrated circuit stack includes adding a first dummy layer to a first contact pad of a circuit, wherein a location of the first dummy layer is determined based on a location of a second contact pad of a connecting substrate. The method further includes converting the first dummy layer location to the connecting substrate. The method further includes adjusting the first dummy layer location in the circuit in response to a determination that the first dummy layer location is misaligned with the second contact pad. The method further includes performing a first layout versus schematic (LVS) check of the connecting substrate including the first dummy layer in response to a determination that the first dummy layer is aligned with the second contact pad.

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

Abstract: A system includes a rack of servers and a fluid circuit for cooling the rack of servers. The fluid circuit includes one or more cooling modules, a heat-exchanging module, and a pump. The one or more cooling modules are thermally connected to a conduit for flowing a coolant therethrough. Each cooling module includes a heat-exchanger thermally connected to the conduit and a chiller fluidly coupled to the heat-exchanger. The heat-exchanging module is fluidly connected to an outlet of the conduit. The pump is configured to drive the coolant from the heat-exchanging module to each server in the rack of servers.

Abstract: The present disclosure describes a semiconductor device that includes a first die bonded to a second die with interconnect structures in the first die. The first die includes a photodiode having first and second electrodes on a first side of a first dielectric layer, and first, second, and third interconnect structures in the first dielectric layer. The first and second interconnect structures are connected to the first and second electrodes, respectively. The second electrode has a polarity opposite to the first electrode. The second and third interconnect structures extend to a second side opposite to the first side of the first dielectric layer. The second die includes a second dielectric layer and a fourth interconnect structure in the second dielectric layer. The second dielectric layer is bonded to the second side of the first dielectric layer. The fourth interconnect structure connects the second and third interconnect structures.

Abstract: A circuit board includes a platform controller hub (PCH), a peripheral component connector and a switch. The PCH includes a clock request pin and a GPIOB pin. The peripheral component connector includes a connector pin. The switch is controlled by the GPIOB pin and is coupled between a low potential and a line between the connector pin and the clock request pin and is configured to: conduct the line and the low potential based on a high potential of the GPIOB pin; and disconnect the line and the low potential based on the low potential of the GPIOB pin.

Abstract: A method of reshaping a severely stenosed aortic valve having leaflets with bicuspid malformation and severe calcification. The method includes delivering a balloon with an expandable distal end to the aortic valve, expanding the balloon so that the distal end of the balloon is expanded to push the leaflets upward from bottom of the aortic valve to reshape the leaflets, and forming a space compliant to a self-expandable interventional valve for release, thereby facilitating the following TAVR procedure, reducing the adverse consequences of the TAVR procedure, and improving the surgical stability and the surgical prognosis.

Abstract: Devices and methods of manufacture for a hybrid interposer within a semiconductor device. A semiconductor device may include a package substrate and a hybrid interposer. The hybrid interposer may include an organic interposer material layer, and a non-organic interposer material layer positioned between the organic interposer material layer and the package substrate. The semiconductor device may further include an integrated device positioned within the hybrid interposer. In one embodiment, the integrated device may be positioned within the organic interposer material layer. In another embodiment, the integrated device may be positioned within the non-organic interposer material layer. In a further embodiment, the integrated device may be positioned within the organic interposer material layer and the non-organic interposer material layer.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: A method includes forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on and extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.

Abstract: A method for forming a package structure is provided. The method includes disposing a semiconductor die over a carrier substrate, wherein a removable film is formed over the semiconductor die, disposing a first stacked die package structure over the carrier substrate, wherein a top surface of the removable film is higher than a top surface of the first stacked die package structure, and removing the removable film to expose a top surface of the semiconductor die, wherein a top surface of the semiconductor die is lower than the top surface of the first stacked die package structure.

Abstract: A semiconductor power device includes a substrate, a channel layer, a barrier layer, a gate, a source, and a drain. The channel layer is located on the substrate. The barrier layer is located on the channel layer and includes a first region and a second region outside the first region. There is a first compound in the first region and a second compound in the second region. The first compound and the second compound each have an aluminum atom of a different ratio, and the aluminum composition ratio of the first compound is less than the aluminum composition ratio of the second compound. The ratio consists of a plurality of different atoms in the first compound and the second compound.

Abstract: A method includes forming a package, which includes forming a plurality of redistribution lines over a carrier, and forming a thermal dissipation block over the carrier. The plurality of redistribution lines and the thermal dissipation block are formed by common processes. The thermal dissipation block has a first metal density, and the plurality of redistribution lines have a second metal density smaller than the first metal density. The method further includes forming a metal post over the carrier, placing a device die directly over the thermal dissipation block, and encapsulating the device die and the metal post in an encapsulant. The package is then de-bonded from the carrier.

Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.

Abstract: A smart speaker including a first light sensor, a second light sensor, a loudspeaker and a processor is provided. The first light sensor is configured to sense the first ambient light brightness value. The second light sensor is configured to sense the second ambient light brightness value. The loudspeaker is configured to emit a sound. The processor is electrically connected to the first light sensor, the second light sensor and the loudspeaker, and is configured to control a sound effect of the sound according to the first ambient light brightness value and the second ambient light brightness value.

Abstract: A package structure is provided. The package structure includes a reinforced plate and multiple conductive structures penetrating through the reinforced plate. The package structure also includes a redistribution structure over the reinforced plate. The redistribution structure has multiple polymer-containing layers and multiple conductive features. The package structure further includes multiple chip structures bonded to the redistribution structure through multiple solder bumps. In addition, the package structure includes a protective layer surrounding the chip structures.

Abstract: A chip package structure is provided. The chip package structure includes a first redistribution structure having a first surface and a second surface opposite to the first surface. The chip package structure includes a first chip over the first surface. The chip package structure includes a first conductive pillar over the first surface and adjacent to the first chip. The chip package structure includes a second chip over the second surface. The chip package structure includes a second conductive pillar over the second surface and adjacent to the second chip. The chip package structure includes a first molding layer over the first surface and surrounding the first chip. The chip package structure includes a second molding layer over the second surface and surrounding the second chip.

Abstract: An embodiment interposer includes a first electrically conducting line structure, an electrically conducting via structure that is electrically connected to the first electrically conducting line structure, and a second electrically conducting line structure formed along with the electrically conducting via structure as a monolithic structure. In some embodiments, a portion of the first electrically conducting line structure may be provided within the electrically conducting via structure such that the first electrically conducting line structure is at least partially overlapping with the electrically conducting via structure such that the first electrically conducting line structure and the electrically conducting via structure share a common surface. In other embodiments, the interposer may further include a via land structure electrically connected to the first electrically conducting line structure.

Abstract: A semiconductor device includes a substrate, a dummy gate structure, and a gate structure. The substrate has a dummy gate trench and a gate trench, and includes a first well region, a second well region and a source region. The first well region is formed by doping at least one element from a first element group, and has a first conductive channel. The second well region is formed by doping at least one element from a second element group, the second well region is on the first well region and has a second conductive channel, a polarity of the second conductive channel is opposite to that of the first conductive channel. The dummy gate structure is in the dummy gate trench of the substrate, and a portion of the dummy gate structure is in the first well region. The gate structure is between the adjacent dummy gate structures.