Abstract: Examples pertaining to re-transmission cyclic redundancy check (CRC) for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) encodes a plurality of information bits using a polar code to generate a polar code block (CB). The apparatus performs one or more transmissions of the polar CB using hybrid automatic repeat request (HARQ) by performing an initial transmission of the polar CB and performing a re-transmission of the polar CB with a re-transmission cyclic redundancy check (ReTX CRC).

Abstract: Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

Abstract: Examples pertaining to bit selection for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) generates a re-transmission polar code block (CB) in a polar incremental redundancy HARQ (IR-HARQ) procedure. The apparatus then transmits the re-transmission polar CB as a re-transmission of an initial transmission of an initial polar code carrying a plurality of information bits. In generating the re-transmission polar CB, the apparatus selects one or more re-transmission information bits from the plurality of information bits.

Abstract: Examples pertaining to additional bit freezing for polar coding are described. An apparatus performs polar coding to encode a plurality of input subblocks of information bits, frozen bits and optional cyclic redundancy check (CRC) bits to generate a plurality of subblocks of coded bits. The apparatus then transmits at least some of the subblocks of coded bits. In performing the polar coding, the apparatus additionally freezes one of the plurality of input subblocks corresponding to one of the interleaved plurality of subblocks of coded bits which decreases polarization gain due to puncturing.

Abstract: Examples pertaining to bit selection for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) generates a re-transmission polar code block (CB) in a polar incremental redundancy HARQ (IR-HARQ) procedure. The apparatus then transmits the re-transmission polar CB as a re-transmission of an initial transmission of an initial polar code carrying a plurality of information bits. In generating the re-transmission polar CB, the apparatus selects one or more re-transmission information bits from the plurality of information bits.

Abstract: Examples pertaining to re-transmission cyclic redundancy check (CRC) for polar coding incremental-redundancy hybrid automatic repeat request (IR-HARQ) are described. An apparatus (e.g., UE) encodes a plurality of information bits using a polar code to generate a polar code block (CB). The apparatus performs one or more transmissions of the polar CB using hybrid automatic repeat request (HARQ) by performing an initial transmission of the polar CB and performing a re-transmission of the polar CB with a re-transmission cyclic redundancy check (ReTX CRC).

Abstract: A method for generating an interleaved polar code is provided and including: performing a channel selection algorithm on message bits to generate an interleaved polar sequence; and performing interleaved encoding on the message bits to generate an interleaved polar code according to the interleaved polar sequence. The process performed at each encoding stage includes an interleaving process and a polar process.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Aspects of the disclosure provide polar code rate matching methods. A first method can include determining whether to puncture or shorten a mother polar code according to a mother code rate and/or a rate matched code rate, and selecting K positions in the sequence of N input bits for input of K information bits to a polar encoder according to an offline prepared index list ordered according to the reliabilities of respective synthesized channels. Frozen input bits caused by puncturing or shortening are skipped during the selection. A second method includes generating a mother polar code, rearranging code bits of the mother polar code to form a rearranged sequence that can be stored in a circular buffer, and performing, in a unified way, one of puncturing, shortening, or repetition on the rearranged sequence to obtain a rate matched code.

Abstract: Concepts and examples pertaining to combined coding design for efficient codeblock extension are described. A processor of a communication apparatus may combine channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme. The processor may also code second codeblocks of a larger size using the second coding scheme.

Abstract: Aspects of the disclosure provide an apparatus that includes a transceiver circuit and a baseband processing circuit. The transceiver circuit is configured to transmit signals that carry a data unit to another apparatus and receive signals that carry a response from the other apparatus. The baseband processing circuit is configured to provide a first digital stream to carry a data unit to the transceiver circuit for transmission, and provide a second digital stream to carry a portion of the data unit to the transceiver circuit for retransmission when the transceiver circuit receives a response that is indicative of a partial receiving failure of the data unit at the other apparatus.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.