Abstract: Aspects of the disclosure provide a method for polar code puncturing. The method can include receiving a mother polar code including a sequence of coded bits, the sequence of coded bits having indices {0, . . . , N?1} and including at least a first block of coded bits having indices {0, . . . , i?1}, a second block of coded bits having indices {i, . . . , i+k?1}, a third block of coded bits having indices {i+k, . . . , i+k+k?1}, interleaving the second block of coded bits with the third block of coded bits to form a rearranged sequence of coded bits including the N coded bits, and extracting the last M coded bits from the rearranged sequence of coded bits to generate a punctured code having a length of M.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer. Alternatively or additionally, the processor may generate the QC-LDPC code including a base matrix a portion of which forming a kernel matrix that corresponds to a code rate of at least a threshold value.

Abstract: A processor of an apparatus selects a codebook from a plurality of codebooks embedded in a quasi-cyclic-low-density parity-check (QC-LDPC) code. The processor stores the selected codebook in a memory associated with the processor. The processor also encodes data using the selected codebook to generate a plurality of modulation symbols of the data. The processor further controls a transmitter of the apparatus to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus. In selecting the codebook from the plurality of codebooks embedded in the QC-LDPC code, the processor selects the codebook according to one or more rules such that a small codebook requiring a shorter amount of processing latency for the encoding is selected for the encoding unless a larger codebook corresponding to a larger amount of processing latency for the encoding is necessary for the encoding.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: A processor of an apparatus establishes a wireless communication link with at least one other apparatus via a transceiver of the apparatus. The processor wirelessly communicates with the other apparatus via the wireless communication link by: selecting a first shift-coefficient table from a plurality of shift-coefficient tables; generating a QC-LDPC code using a base matrix and at least a portion of the first shift-coefficient table; selecting a codebook from a plurality of codebooks embedded in the QC-LDPC code; storing the selected codebook in a memory associated with the processor; encoding data using the selected codebook to generate a plurality of modulation symbols of the data; and controlling the transceiver to multiplex, convert, filter, amplify and radiate the modulation symbols as electromagnetic waves through one or more antennas of the apparatus to transmit the modulation symbols of the data to the other apparatus via the wireless communication link.

Abstract: Concepts and schemes pertaining to structure of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide encoded data. A transceiver of the apparatus transmits the encoded data to at least one network node of a wireless network. In encoding the data to provide the encoded data, the processor encodes the data to result in each code block in the encoded data comprising a respective bit-level interleaver.

Abstract: Concepts and schemes pertaining to location of interleaver with low-density parity-check (LDPC) code are described. A processor of an apparatus encodes data to provide a stream of encoded data. The processor also rate matches the encoded data to provide a rate-matched stream of encoded data. The processor further interleaving the rate-matched stream of encoded data. In rate matching the encoded data, the processor buffers the stream of encoded data in a circular buffer, with the circular buffer functioning as a rate matching block that rate matches the stream of encoded data. In interleaving the rate-matched stream of encoded data, the processor performs bit-level interleaving on the rate-matched stream of encoded data to provide a stream of interleaved data.

Abstract: Concepts and schemes pertaining to shift coefficient and lifting factor design for NR LDPC code are described. A processor of an apparatus may generate a quasi-cyclic-low-density parity-check (QC-LDPC) code and encode data using the selected codebook. In generating the QC-LDPC code, the processor may define a plurality of sets of lifting factors, generate a respective table of shift values for each lifting factor of the plurality of sets of lifting factors, and generate the QC-LDPC code using a base matrix and the shift coefficient table.

Abstract: A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas, and activating a second group of the antennas when the apparatus is configured in the single component carrier. T the first group of antennas are configured for a first part of the processing engines and the second group of antennas are configured for a second part of the processing engines, and the first part of the processing engines and the second part of the processing engines share a MIMO detector.

Abstract: Concepts and schemes pertaining to information coding for mobile communications are described. A processor of an apparatus encodes data to provide encoded data. The processor also transmits the encoded data to a network node of a wireless network. In encoding the data, the processor encodes the data with a low-density parity-check (LDPC) code to provide LDPC-coded data. Moreover, the processor processes the LDPC-coded data with a forward error correction (FEC) robustness enhancement function to provide the encoded data. The FEC robustness enhancement function includes an interleaving function that interleaves the LDPC-coded data to provide the encoded data, an interlacing function that interlaces the LDPC-coded data to provide the encoded data, or a bit-reordering function that reorders bits of the LDPC-coded data to provide the encoded data.

Abstract: Concepts and examples pertaining to combined coding design for efficient codeblock extension are described. A processor of a communication apparatus may combine channel polarization of a communication channel with a first coding scheme for first codeblocks of a smaller size to generate a second coding scheme. The processor may also code second codeblocks of a larger size using the second coding scheme.

Abstract: Aspects of the disclosure provide polar code rate matching methods. A first method can include determining whether to puncture or shorten a mother polar code according to a mother code rate and/or a rate matched code rate, and selecting K positions in the sequence of N input bits for input of K information bits to a polar encoder according to an offline prepared index list ordered according to the reliabilities of respective synthesized channels. Frozen input bits caused by puncturing or shortening are skipped during the selection. A second method includes generating a mother polar code, rearranging code bits of the mother polar code to form a rearranged sequence that can be stored in a circular buffer, and performing, in a unified way, one of puncturing, shortening, or repetition on the rearranged sequence to obtain a rate matched code.

Abstract: Aspects of the disclosure provide a method for polar code puncturing. The method can include receiving a mother polar code including a sequence of coded bits, the sequence of coded bits having indices {0, . . . , N?1} and including at least a first block of coded bits having indices {0, . . . , i?1}, a second block of coded bits having indices {i, . . . , i+k?1}, a third block of coded bits having indices {i+k, i+k+k?1}, interleaving the second block of coded bits with the third block of coded bits to form a rearranged sequence of coded bits including the N coded bits, and extracting the last M coded bits from the rearranged sequence of coded bits to generate a punctured code having a length of M.

Abstract: Concepts and schemes pertaining to quasi-cyclic-low-density parity-check (QC-LDPC) coding are described. A processor of an apparatus may generate a QC-LDPC code having a plurality of codebooks embedded therein. The processor may select a codebook from the plurality of codebooks. The processor may also encode data using the selected codebook. Alternatively or additionally, the processor may generate the QC-LDPC code including at least one quasi-row orthogonal layer.

Abstract: A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas, and activating a second group of the antennas when the apparatus is configured in the single component carrier. T the first group of antennas are configured for a first part of the processing engines and the second group of antennas are configured for a second part of the processing engines, and the first part of the processing engines and the second part of the processing engines share a MIMO detector.

Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

Abstract: An apparatus for interference cancellation includes: a front end processing circuit, for receiving at least an interference signal and a desire signal; an inner processing circuit, for channel/noise estimation and for suppressing the interference signal; and a MIMO (multi-input multi-output) processing circuit, for blindly detecting an interference parameter of the interference signal based on the suppressed interference signal, and for jointly cancelling the interference signal from the desire signal and for demodulating the desire signal based on the detected interference parameter and the channel/noise estimation from the inner processing circuit.

Abstract: A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas; and activating a second group of the antennas if the apparatus is configured in the single component carrier.

Abstract: A communications apparatus and method are provided. The communications method for an apparatus capable of Carrier Aggregation (CA), wherein the apparatus includes a plurality of processing engines and antennas, includes the steps of determining whether the apparatus is configured in a single component carrier for a first group of the antennas; and activating a second group of the antennas if the apparatus is configured in the single component carrier.

Abstract: A superimposed network coding method, that is applicable to communication in a network, containing a first, a second, and a third network nodes, comprising following steps: firstly, the first network node transmits its first data to the second, and the third network nodes, so that the second and the third network nodes receive corresponding signals; next, the second network node transmits its second data to the first and the third network nodes, so that the first and the third network nodes receive the corresponding signal; then, the third network node superimposes and sums signals received with summation weights to generate a superimposed signal, and transmits it to the first and the second network nodes; finally, the first and the second network nodes delete their own data from signals received, and then demodulate the signals received to obtain the second data and the first data.