Abstract: A communication device for handling a reception of a multicast broadcast service (MBS) transmission and a small data transmission (SDT) includes: triggering the SDT with a network, when at least one triggering condition is satisfied, wherein the at least one triggering condition comprises that the communication device is not receiving first downlink (DL) data associated with the MBS transmission; transmitting uplink (UL) data associated with the SDT to the network or receiving second DL data associated with the SDT from the network; and receiving a radio resource control (RRC) message from the network to terminate the SDT.

Abstract: A catalyst includes 1 part by mole of a palladium complex and 500 to 10000 parts by mole of an amine compound. The palladium complex has a chemical structure of ?in which X is halogen, each of R1 is independently C1-8 linear alkyl group or C3-8 cycloalkyl group, and each of R2 is independently H or C1-4 alkyl group.

Abstract: A syringe base includes a base body, an abutting component and at least one engaging component. The base body includes a position-limiting portion and has a position-limiting chamber and a support channel. The position-limiting chamber adjoins the position-limiting portion. The support channel is in communication with the position-limiting chamber and penetrates the base body. The abutting component is disposed at an end of the base body and has a base opening and a position-limiting component slot. The base opening is in communication with the support channel. The position-limiting component slot is disposed outside the base opening and adjoins the position-limiting chamber. The engaging component is disposed at the abutting component, protrudes relative to the abutting component and is adapted to bend or rotate relative to the abutting component. A syringe support and a syringe assembly are further provided.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

Abstract: A method for processing an integrated circuit includes forming first and second gate all around transistors. The method forms a dipole oxide in the first gate all around transistor without forming the dipole oxide in the second gate all around transistor. This is accomplished by entirely removing an interfacial dielectric layer and a dipole-inducing layer from semiconductor nanosheets of the second gate all around transistor before redepositing the interfacial dielectric layer on the semiconductor nanosheets of the second gate all around transistor.

Abstract: A method for processing an integrated circuit includes forming N-type and P-type gate all around transistors and core gate all around transistors. The method deposits a first metal gate layer for the P-type transistors and a second metal gate layer for the N-type transistors. The method forms a passivation layer in-situ with the metal gate layer of the P-type transistors.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first nanostructures formed over a substrate, and a plurality of second nanostructures formed over the substrate. The semiconductor device includes a gate structure surrounding the first nanostructures and the second nanostructures, and the first hard mask layer and the second hard mask layer are surrounded by the gate dielectric layer. The semiconductor device includes an isolation structure extending upwardly above the substrate, and a bottom surface of the isolation structure is lower than a bottommost surface of the gate structure.

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a first channel region in a first region and over a second channel region in a second region; introducing a first dipole element into the first dielectric layer in the first region to form a first dipole-containing gate dielectric layer in the first region; forming a second dielectric layer over the first dipole-containing gate dielectric layer; introducing fluorine into the second dielectric layer to form a first fluorine-containing gate dielectric layer over the first dipole-containing gate dielectric layer; and forming a gate electrode over the first fluorine-containing gate dielectric layer.

Abstract: Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

Abstract: Provided is the use of an effective amount of alpha-enolase (enolase-1, ENO-1) antagonist in manufacturing a medicament for treating a fibrotic disease. ENO-1 antagonist significantly attenuated body weight loss and lung weight gain as well as the fibrosis lesion and collagen deposition in lungs. Also, ENO-1 antagonist significantly reduced cell migration and secretion of collagen and TGF-? in primary mouse lung myofibroblasts.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A device includes a substrate, and a first semiconductor channel over the substrate. The first semiconductor channel includes a first nanosheet of a first semiconductor material, a second nanosheet of a second semiconductor material in physical contact with a topside surface of the first nanosheet, and a third nanosheet of the second semiconductor material in physical contact with an underside surface of the first nanosheet. The first gate structure is over and laterally surrounding the first semiconductor channel, and in physical contact with the second nanosheet and the third nanosheet.

Abstract: A pair of crimping pliers is provided. The crimping pliers include a large handle, a small handle, a connecting rod, and a clamp fixing plate that form a hinged four-rod mechanism. Two ends of the connecting rod are connected between a rear part of the large handle and a rear part of the small handle. The clamp fixing plate is connected between a front part of the large handle and a front part of the small handle. A rear part of the connecting rod is bent and extends towards a tail end of the large handle, thereby extending a force arm. A first returning spring is connected between a back side of a bent part of the clamp fixing plate and the large handle. A pawl is rotatable and installed at the large handle. The pawl matches and meshes with outer pawl teeth of the clamp fixing plate.

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary method includes forming a gate dielectric layer around first channel layers in a p-type gate region and around second channel layers in an n-type gate region. Sacrificial features are formed between the second channel layers in the n-type gate region. A p-type work function layer is formed over the gate dielectric layer in the p-type gate region and the n-type gate region. After removing the p-type work function layer from the n-type gate region, the sacrificial features are removed from between the second channel layers in the n-type gate region. An n-type work function layer is formed over the gate dielectric layer in the n-type gate region. A metal fill layer is formed over the p-type work function layer in the p-type gate region and the n-type work function layer in the n-type gate region.

Abstract: A method for forming a semiconductor arrangement comprises forming a first fin in a semiconductor layer. A first gate dielectric layer includes a first high-k material is formed over the first fin. A first sacrificial gate electrode is formed over the first fin. A dielectric layer is formed adjacent the first sacrificial gate electrode and over the first fin. The first sacrificial gate electrode is removed to define a first gate cavity in the dielectric layer. A second gate dielectric layer including a second dielectric material different than the first high-k material is formed over the first gate dielectric layer in the first gate cavity. A first gate electrode is formed in the first gate cavity over the second gate dielectric layer.

Abstract: A structure has stacks of semiconductor layers over a substrate and adjacent a dielectric feature. A gate dielectric is formed wrapping around each layer and the dielectric feature. A first layer of first gate electrode material is deposited over the gate dielectric and the dielectric feature. The first layer on the dielectric feature is recessed to a first height below a top surface of the dielectric feature. A second layer of the first gate electrode material is deposited over the first layer. The first gate electrode material in a first region of the substrate is removed to expose a portion of the gate dielectric in the first region, while the first gate electrode material in a second region of the substrate is preserved. A second gate electrode material is deposited over the exposed portion of the gate dielectric and over a remaining portion of the first gate electrode material.

Abstract: A semiconductor device according to the present disclosure includes a fin structure over a substrate, a vertical stack of silicon nanostructures disposed over the fin structure, an isolation structure disposed around the fin structure, a germanium-containing interfacial layer wrapping around each of the vertical stack of silicon nanostructures, a gate dielectric layer wrapping around the germanium-containing interfacial layer, and a gate electrode layer wrapping around the gate dielectric layer.

Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first semiconductor nanostructures formed over a substrate, and a first S/D structure formed on sidewall surfaces of the first semiconductor nanostructures. The semiconductor device includes a plurality of second semiconductor nanostructures formed over the substrate, and a second S/D structure formed on sidewall surfaces of the second semiconductor nanostructures. The semiconductor device includes an isolation structure formed between the first S/D structure and the second S/D structure, and the isolation structure has a first sidewall surface in direct contact with the first S/D structure and a second sidewall surface in direct contact with the second S/D structure.