Patents by Inventor Mao-song Tseng
Mao-song Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9153675Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.Type: GrantFiled: August 23, 2013Date of Patent: October 6, 2015Assignee: MOSEL VITALEC INC.Inventors: Chien-Ping Chang, Chien-Chung Chu, I-Hsien Tang, Chon-Shin Jou, Mao-Song Tseng, Shin-Chi Lai
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Publication number: 20140327038Abstract: A power semiconductor includes a semiconductor substrate, a metal oxide semiconductor layer, a N-type buffer layer and a P-type injection layer. The semiconductor substrate has a first surface and a second surface. The metal oxide semiconductor layer is formed on the first surface for defining a N-type drift layer of the semiconductor substrate. The N-type buffer layer is formed on the second surface through ion implanting, and the P-type injection layer is formed on the N-type buffer layer through ion implanting. By utilizing the semiconductor substrate having drift layer and forming the N-type buffer layer and the P-type injection layer on the second surface of the semiconductor substrate through ion implanting, the ion concentration is adjustable. As a result, the electron hole injection efficiency and the width of depletion region are easily adjusted, the fabricating processes are simplified, and the fabricating time and cost are reduced.Type: ApplicationFiled: August 23, 2013Publication date: November 6, 2014Applicant: Mosel Vitalec Inc.Inventors: Chien-Ping Chang, Chien-Chung Chu, I-Hsien Tang, Chon-Shin Jou, Mao-Song Tseng, Shin-Chi Lai
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Patent number: 7615442Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.Type: GrantFiled: November 30, 2006Date of Patent: November 10, 2009Assignee: Mosel Vitelic Inc.Inventors: Hsin-Huang Hsieh, Mao-Song Tseng, Chien-Ping Chang
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Patent number: 7402522Abstract: A hard mask structure is disclosed. The hard mask structure is used for manufacturing a deep trench of a super-junction device having a substrate and an epitaxial layer formed on the substrate. The hard mask structure comprises an ion barrier layer formed on the epitaxial layer for blocking ions from diffusing into the epitaxial layer, and a deposition layer formed on the ion barrier layer. Thereby, the deep trench of the super-junction device is formed by performing an etch process on the epitaxial layer via the hard mask structure. The hard mask structure can effectively prevent ions from diffusing into the epitaxial layer, so as to avoid unusual electrical property.Type: GrantFiled: March 10, 2006Date of Patent: July 22, 2008Assignee: Mosel Vitelic Inc.Inventors: Hsing Huang Hsieh, Chien Ping Chang, Mao Song Tseng
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Patent number: 7271048Abstract: A method of manufacturing a trench MOSFET with high cell density is disclosed. The method introduces a sidewall oxide spacer for narrowing the opening of the trench structure, thereby decreasing the cell pitch of the memory units. Moreover, the source structure is formed automatically by means of an extra contact silicon etch for preventing the photoresist from lifting during the ion implantation of the prior art. On the other hand, the contact structure is filled with W-plug for overcoming the defect of poor metal step coverage resulted from filling the contact structure with AlSiCu according to the prior art. Thus, the cell density of the device can be increased; and the Rds-on and the power loss of the device can be decreased.Type: GrantFiled: August 12, 2005Date of Patent: September 18, 2007Assignee: Mosel Vitelic, Inc.Inventors: Chien-Ping Chang, Mao Song Tseng, Hsin Huang Hsieh, Tien-Min Yuan
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Patent number: 7265024Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.Type: GrantFiled: January 10, 2006Date of Patent: September 4, 2007Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng
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Publication number: 20070134882Abstract: A method for fabricating a trench metal-oxide-semiconductor field effect transistor is disclosed. The method comprises steps of providing a substrate with an epitaxy layer thereon and etching the epitaxy layer to form a trench structure; forming a gate oxide layer on the surface of the epitaxy layer and the inner sidewalls of the trench structure and depositing a polysilicon layer to fill the trench structure; introducing a nitrogen gas and performing a driving-in procedure to form a body structure; performing an implantation procedure to form a source layer; forming a dielectric layer on the trench structure and the source layer; etching the dielectric layer and the source layer to define a source structure and form a contact region; filling the contact region with a contact structure layer; and forming a conductive metal layer on the contact structure layer and the dielectric layer.Type: ApplicationFiled: November 30, 2006Publication date: June 14, 2007Applicant: MOSEL VITELIC INC.Inventors: Hsin-Huang Hsieh, Mao-Song Tseng, Chien-Ping Chang
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Patent number: 7205196Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.Type: GrantFiled: January 14, 2005Date of Patent: April 17, 2007Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chien-Ping Chang, Mao-Song Tseng, Tien-Min Yuan
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Publication number: 20060186465Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.Type: ApplicationFiled: January 10, 2006Publication date: August 24, 2006Applicant: MOSEL VITELIC, INC.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng
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Patent number: 7087958Abstract: In one embodiment of the invention, a semiconductor device set includes at least one trench-typed MOSFET and a trench-typed termination structure. The trench-typed MOSFET has a trench profile and includes a gate oxide layer in the trench profile, and a polysilicon layer on the gate oxide layer. The trench-typed termination structure has a trench profile and includes an oxide layer in the trench profile. A termination polysilicon layer with discrete features separates the termination polysilicon layer. An isolation layer covers the termination polysilicon layer and filling the discrete features. The trench-typed MOSFET and the trench-typed termination structure may be formed on a DMOS device including an N+ silicon substrate, an N epitaxial layer on the N+ silicon substrate, and a P epitaxial layer on the N epitaxial layer. The trench profiles of the trench-typed MOSFET and of the trench-typed termination structure may penetrate through the P epitaxial layer into the N epitaxial layer.Type: GrantFiled: February 3, 2004Date of Patent: August 8, 2006Assignee: Mosel Vitelic, Inc.Inventors: Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng, Hsing-Huang Hsieh
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Patent number: 7084457Abstract: A DMOS device having a trench bus structure thereof is introduced. The trench bus structure comprises a field oxide layer formed on a P substrate, and a trench extending from an top surface of the field oxide layer down to a lower portion of the P substrate. A gate oxide layer and a polysilicon bus are formed to fill the trench as a main portion of the bus structure. In addition, an isolation layer and a metal line are formed atop the polysilicon bus and the field oxide layer. An opening is formed in the isolation layer to form connections between the polysilicon bus and the metal line. In specific embodiments, the bus trench and the gate trenches of the DMOS device are formed simultaneously, and the polysilicon bus and the gate electrode are formed simultaneously as well. Therefore, the bus structure is able to form the DMOS transistor without demanding any lithographic step for defining the position of the polysilicon bus.Type: GrantFiled: February 5, 2004Date of Patent: August 1, 2006Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng
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Publication number: 20060046389Abstract: The present invention provides a manufacturing process and the structure of an integrated circuit. In one embodiment, one polysilicon layer deposition and one polysilicon layer etching are used to form the gate of a trench device and the polysilicon layer of a planar device simultaneously. The present invention not only has overcome the problem of the electric leakage, but also has the advantages of withstanding a higher voltage, reducing the relevant cost and increasing the yields. The present invention possesses the outstanding technical features in the field of the power device.Type: ApplicationFiled: January 14, 2005Publication date: March 2, 2006Applicant: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chien-Ping Chang, Mao-Song Tseng, Tien-Min Yuan
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Patent number: 6998315Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.Type: GrantFiled: February 11, 2005Date of Patent: February 14, 2006Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Su-Wen Chang, Mao-Song Tseng
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Patent number: 6989306Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region.Type: GrantFiled: February 3, 2004Date of Patent: January 24, 2006Assignee: Mosel Vitelic, Inc.Inventors: Chiao-Shun Chuang, Hsin-Huang Hsieh, Mao-Song Tseng, Chien-Ping Chang
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Publication number: 20050199952Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.Type: ApplicationFiled: February 11, 2005Publication date: September 15, 2005Applicant: MOSEL VITELIC, INC.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Su-Wen Chang, Mao-Song Tseng
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Patent number: 6855986Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.Type: GrantFiled: August 28, 2003Date of Patent: February 15, 2005Assignee: Mosel Vitelic, Inc.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Su-Wen Chang, Mao-Song Tseng
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Publication number: 20050009277Abstract: Embodiments of the invention provide a termination structure of DMOS device and a method of forming the same. In forming the termination structure, a silicon substrate with an epitaxial layer formed thereon is provided. A body region defined by doping the epitaxial layer is then selectively etched to form a plurality of DMOS trenches therein. Thereafter, a gate oxide layer is formed over exposed surfaces in the body region and a termination oxide layer is formed to encircle the body region. Afterward, a polysilicon layer is deposited over all the exposed surfaces, and then selectively etched to form a plurality of poly gates in the DMOS trenches and a polysilicon plate having an extending portion toward the body region over the termination oxide layer. By using the termination polysilicon layer as an implantation mask, sources are formed in the body region.Type: ApplicationFiled: February 3, 2004Publication date: January 13, 2005Applicant: MOSEL VITELIC, INC.Inventors: Chiao-Shun Chuang, Hsin-Huang Hsieh, Mao-Song Tseng, Chien-Ping Chang
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Patent number: 6828196Abstract: Embodiments of the present invention relate to a process for filling a trench structure of a semiconductor device to prevent formation of voids in the trench structure so as to minimize current leakage and provide excellent electrical properties. In one embodiment, a process for filling a trench of a semiconductor device comprises providing a semiconductor substrate; forming a silicon nitride layer on the semiconductor substrate; forming an oxide layer on the silicon nitride layer; partially removing the oxide layer, the silicon nitride layer and the semiconductor substrate to form at least one trench; forming a sacrificial oxide layer on sidewalls of the trench; removing the sacrificial oxide layer; performing an etching procedure to remove portions of the silicon nitride layer protruding from the sidewalls of the trench so as to form substantially even sidewalls of the trench; and forming a trench-fill layer to fill the trench and deposit on the oxide layer.Type: GrantFiled: August 28, 2003Date of Patent: December 7, 2004Assignee: Mosel Vitelec, Inc.Inventors: Pei-Feng Sun, Shih-Chi Lai, Mao-Song Tseng, Yi-Fu Chung
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Patent number: 6821913Abstract: Embodiments of the present invention are directed to an improved method for forming dual oxide layers at the bottom of a trench of a substrate. A substrate has a trench which includes a bottom and a sidewall. The trench may be created by forming a mask oxide layer on the substrate; defining the mask oxide layer to form a patterned mask oxide layer and exposing a partial surface of the substrate to form a window; and using the patterned mask oxide layer as an etching mask to form the trench in the window. A first oxide layer is formed on the sidewall and the bottom of the trench of the substrate. A photoresist layer is formed on the substrate, filling the trench of the substrate. The method further comprises partially etching back the photoresist layer to leave a remaining photoresist layer in the trench. The height of the remaining photoresist layer is lower than the depth of the trench. A curing treatment of the remaining photoresist layer is performed after the partial etching.Type: GrantFiled: August 29, 2002Date of Patent: November 23, 2004Assignee: Mosel Vitelic, Inc.Inventors: Chiao-Shun Chuang, Chien-Ping Chang, Mao-Song Tseng, Cheng-Tsung Ni
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Publication number: 20040222458Abstract: Embodiments of the present invention are directed to a termination structure provided for a trench DMOS device to reduce occurrence of current leakage resulting from electric field crowding at the border of the active area and a method of manufacturing the same. In one embodiment, the termination structure for the trench DMOS device comprises a substrate of a first type conductivity and an epitaxial layer of the first type conductivity over the substrate. The epitaxial layer has a lower doping concentration than the substrate. A body region of a second type conductivity is provided within the epitaxial layer. A trench extends through the body region between an active area and an edge of the substrate. A gate oxide layer lines the trench and extends to the upper surface of the body region between the trench and the active area. A passivation layer is formed on the gate oxide layer, including sidewalls and a bottom surface of the trench.Type: ApplicationFiled: August 28, 2003Publication date: November 11, 2004Applicant: MOSEL VITELIC, INC.Inventors: Hsin-Huang Hsieh, Chiao-Shun Chuang, Su-Wen Chang, Mao-Song Tseng