Patents by Inventor Mao Zeng
Mao Zeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10706316Abstract: A method of generating a feature descriptor includes determining a first output histogram of an input by processing a first group of pixels of the input to determine first contributions to bins of the first output histogram. The input image including gradient orientation values and gradient magnitude values of a portion of an image that is in a region of a detected feature. After processing the first group of pixels, the method includes determining a second output histogram of the input by processing a second group of pixels of the input to determine second contributions to bins of the second output histogram.Type: GrantFiled: September 27, 2018Date of Patent: July 7, 2020Assignee: QUALCOMM IncorporatedInventors: Kim-Chyan Gan, Mao Zeng, Erich Plondke
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Publication number: 20190095748Abstract: A method of generating a feature descriptor includes determining a first output histogram of an input by processing a first group of pixels of the input to determine first contributions to bins of the first output histogram. The input image including gradient orientation values and gradient magnitude values of a portion of an image that is in a region of a detected feature. After processing the first group of pixels, the method includes determining a second output histogram of the input by processing a second group of pixels of the input to determine second contributions to bins of the second output histogram.Type: ApplicationFiled: September 27, 2018Publication date: March 28, 2019Inventors: Kim-Chyan Gan, Mao Zeng, Erich Plondke
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Patent number: 9823928Abstract: An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.Type: GrantFiled: September 30, 2011Date of Patent: November 21, 2017Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Lucian Codrescu, Erich James Plondke, Ajay Anant Ingle
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Patent number: 9785434Abstract: An apparatus, system and method of determining an extremum are disclosed. A reference location identifier and a reference extremum are coupled. An input extremum of an input data set is determined and a corresponding location identifier of the input extremum is also determined. The input extremum is compared with the reference extremum to determine an output extremum and output location identifier, based on the comparison.Type: GrantFiled: September 23, 2011Date of Patent: October 10, 2017Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Swaminathan Balasubramanian, David J. Hoyle
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Patent number: 9626579Abstract: A method includes receiving image data and performing a non-maximum suppression (NMS) operation on the image data. The method also includes initiating an edge tracking by hysteresis (ETH) operation on a portion of the image data prior to completion of the NMS operation.Type: GrantFiled: May 5, 2014Date of Patent: April 18, 2017Assignee: QUALCOMM IncorporatedInventors: Kim-Chyan Gan, Mao Zeng, Lucian Codrescu
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Publication number: 20170046156Abstract: Systems and methods pertain to looking up entries of a table. A processor receives one or more single instruction multiple data (SIMD) instructions, including a first SIMD instruction which specifies a first subset of indices. A first subset of table entries is looked up, using a crossbar, with the first subset of indices. A first vector output of the first SIMD instruction is based on whether the outputs of the crossbar belong to a desired subset of table entries. Similarly, second, third, and fourth SIMD instructions specify corresponding second, third, and fourth subsets of indices to lookup the remaining table entries using the crossbar. The size of the crossbar is based on the number of indices in the subset of indices used to lookup table entries.Type: ApplicationFiled: August 14, 2015Publication date: February 16, 2017Inventors: Eric Wayne MAHURIN, Lucian CODRESCU, Erich James PLONDKE, David HOYLE, Mao ZENG, Kim-Chyan GAN
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Patent number: 9455743Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.Type: GrantFiled: May 27, 2014Date of Patent: September 27, 2016Assignee: Qualcomm IncorporatedInventors: Bo Zhou, Mao Zeng, Erich James Plondke, Lucian Codrescu, Shu Xiao, Junchen Du, Suhail Jalil
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Publication number: 20150349796Abstract: A method includes executing, at a processor, a dedicated arithmetic encoding instruction. The dedicated arithmetic encoding instruction accepts a plurality of inputs including a first range, a first offset, and a first state and produces one or more outputs based on the plurality of inputs. The method also includes storing a second state, realigning the first range to produce a second range, and realigning the first offset to produce a second offset based on the one or more outputs of the dedicated arithmetic encoding instruction.Type: ApplicationFiled: May 27, 2014Publication date: December 3, 2015Applicant: QUALCOMM IncorporatedInventors: Bo Zhou, Mao Zeng, Erich James Plondke, Lucian Codrescu, Shu Xiao, Junchen Du, Suhail Jalil
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Publication number: 20150317532Abstract: A method includes receiving image data and performing a non-maximum suppression (NMS) operation on the image data. The method also includes initiating an edge tracking by hysteresis (ETH) operation on a portion of the image data prior to completion of the NMS operation.Type: ApplicationFiled: May 5, 2014Publication date: November 5, 2015Applicant: QUALCOMM IncorporatedInventors: Kim-Chyan Gan, Mao Zeng, Lucian Codrescu
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Patent number: 9147123Abstract: A system and method of processing an image is disclosed. A particular method of determining whether a particular pixel of an image is a feature includes receiving data corresponding to a plurality of pixels (from the image) surrounding the particular pixel. The method further includes determining a set of comparison results, each corresponding to one of the plurality of pixels and indicating a result of comparing an attribute value corresponding to one of the plurality of pixels to a comparison value (based on a particular attribute value of the particular pixel and a threshold value). The method further includes performing a processor-executable instruction that, when executed by a processor, causes the processor to identify a subset of the set of comparison results that indicate the particular pixel is the feature. The identified subset may be a consecutive order of pixels of the plurality of pixels.Type: GrantFiled: September 4, 2012Date of Patent: September 29, 2015Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Erich James Plondke, Lucian Codrescu
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Patent number: 9130786Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.Type: GrantFiled: March 15, 2013Date of Patent: September 8, 2015Assignee: Qualcomm IncorporatedInventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
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Patent number: 8990543Abstract: In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.Type: GrantFiled: March 11, 2008Date of Patent: March 24, 2015Assignee: QUALCOMM IncorporatedInventors: Lucian Codrescu, Robert Allan Lester, Charles Joseph Tabony, Erich James Plondke, Mao Zeng, Suresh Venkumahanti, Ajay Anant Ingle
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Publication number: 20150052330Abstract: In a particular embodiment, a method includes executing a vector instruction at a processor. The vector instruction includes a vector input that includes a plurality of elements. Executing the vector instruction includes providing a first element of the plurality of elements as a first output. Executing the vector instruction further includes performing an arithmetic operation on the first element and a second element of the plurality of elements to provide a second output. Executing the vector instruction further includes storing the first output and the second output in an output vector.Type: ApplicationFiled: August 14, 2013Publication date: February 19, 2015Applicant: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Marc Murray Hoffman, Deepak Mathew, Mao Zeng
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Patent number: 8953893Abstract: A system and method of processing an image is disclosed. A particular method of determining whether a particular pixel of an image is a feature candidate includes receiving data corresponding to a subset of a plurality of pixels surrounding the particular pixel. Each of the plurality of pixels may be from the image. The method further includes excluding the particular pixel from consideration as a feature candidate based on a comparison of values of the data to a comparison value. The comparison value may be based on an attribute value of the particular pixel and a threshold attribute value.Type: GrantFiled: September 4, 2012Date of Patent: February 10, 2015Assignee: QUALCOMM IncorporatedInventors: Mao Zeng, Erich James Plondke, Lucian Codrescu
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Patent number: 8855446Abstract: A set of even interpolated sub-pixels is formed based on a pixel window and a tap coefficient register having a tap coefficient set, the pixel window is shifted and, applying the tap coefficient register a set of odd interpolated pixels is formed. The set of even interpolated sub-pixels and the set of odd interpolated sub-pixels are accumulated, repeatedly, until a termination condition is let. In the accumulating, the tap coefficient register is updated with another tap coefficient set, the pixel window is shifted, and the even interpolated pixels are incremented, the pixel window is then shifted again and the odd interpolated pixels are incremented.Type: GrantFiled: April 19, 2012Date of Patent: October 7, 2014Assignee: QUALCOMM IncorporatedInventors: Bo Zhou, Mao Zeng, Junchen Du, Lucian Codrescu, Suhail Jalil
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Patent number: 8843730Abstract: An apparatus includes a processor and a memory coupled to the processor. The memory stores an instruction packet (e.g., a VLIW instruction packet) including a first predicate independent instruction and a second predicate independent instruction. Each of the predicate independent instructions has the same destination.Type: GrantFiled: September 9, 2011Date of Patent: September 23, 2014Assignee: QUALCOMM IncorporatedInventors: Erich J. Plondke, Lucian Codrescu, Mao Zeng, Charles Joseph Tabony, Suresh K. Venkumahanti
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Publication number: 20140270017Abstract: An apparatus includes selection logic configured to select a first subset of a first set of samples stored at a first set of registers. The first subset includes a first sample stored at a first register of the first set of registers and further includes a second sample stored at a second register of the first set of registers. The apparatus further includes shift logic configured to shift a second set of samples stored at a second set of registers. The apparatus further includes a channel estimator configured to generate a first value associated with a channel estimate based on the first subset and further based on a second subset of the shifted second set of samples.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Deepak Mathew, Ajay Anant Ingle, Mao Zeng, Marc M. Hoffman
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Patent number: 8812516Abstract: A method includes executing an instruction at a processor, where executing the instruction includes comparing a data value of a plurality of data values to a first element stored at a first location of a storage device. When the data value satisfies a condition with respect to the first element, the method includes moving the first element to a second location of the storage device and inserting the data value into the first location of the storage device.Type: GrantFiled: October 18, 2011Date of Patent: August 19, 2014Assignee: QUALCOMM IncorporatedInventors: Ajay Anant Ingle, Mao Zeng
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Patent number: 8787422Abstract: A method includes executing a first instruction at a processor to perform a first fast Fourier transform (FFT) operation on a set of inputs in a time domain to produce data in a frequency domain, where the set of inputs is in a first order and where the data in the frequency domain is in a second order. The method also includes performing an operation on the data in the frequency domain to produce data in the frequency domain, where the data in the frequency domain is in the second order. The method includes executing a second instruction at the processor to perform a second FFT operation on the data in the frequency domain to produce data in the time domain, where the data in the time domain is in the first order.Type: GrantFiled: December 13, 2011Date of Patent: July 22, 2014Assignee: QUALCOMM IncorporatedInventors: Marc M. Hoffman, Ajay Anant Ingle, Mao Zeng
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Patent number: 8631056Abstract: In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.Type: GrantFiled: January 9, 2008Date of Patent: January 14, 2014Assignee: QUALCOMM IncorporatedInventors: Shankar Krithivasan, Erich James Plondke, Lucian Codrescu, Mao Zeng