Abstract: A computer system is provided including a local memory, a local bus coupled to the local memory, a peripheral bus and a direct memory access (DMA) controller. The DMA controller performs DMA transfers of data between the local bus and the peripheral bus. The DMA includes a DMA queue for storing data to be transferred and a bus ownership status circuit for determining bus ownership status of the DMA controller. The DMA controller further includes a local bus interface circuit coupled to the DMA queue and to the status circuit for halting the transfer of data from the local bus to the DMA queue without relinquishing DMA ownership over the local bus when the DMA queue is full and the status circuit indicates that the DMA controller has ownership over both the peripheral bus and the local bus.

Abstract: A method and apparatus for interfacing a device which is compliant to a first bus protocol to a second bus having a second protocol and for providing virtual functions through an intelligent bridge. The interface apparatus is coupled to the first bus and the second bus. The interface device detects a configuration cycle on the second bus and translates the configuration cycle into a corresponding cycle in a format understandable by the first bus. The bus cycle is executed on the first bus. A local processor is interrupted by the interface apparatus. A verification and correction program is executed by the local processor to restore configuration header values if the executed bus cycle violated the protocol of the second bus. The interface apparatus insures that requests for access to the first bus are blocked during the execution of the verification and correction program.