Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Abstract: An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.

Abstract: An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed herein.

Abstract: A method of forming a packaged semiconductor device includes providing a conductive frame structure. The conductive frame structure includes a first frame having leadfingers configured for directly attaching to a semiconductor device, such as an integrated power semiconductor device that includes both power devices and logic type devices. The leadfingers are further configured to provide high current capacity and a high thermal dissipation capacity for the power device portion of the semiconductor device. In one embodiment, the conductive frame structure further includes a second frame joined to the first frame. The second frame includes a plurality of leads configured to electrically connect to low power device portions of the semiconductor device. A package body is formed to encapsulate the semiconductor device and at least portions of the leadfingers and leads.

Abstract: A packaged electronic device includes an integrated antenna as part of a conductive leadframe. The conductive leadframe includes a die paddle have an elongated conductive beam structure configured as a transmission line, and a ground plane structure disposed surrounding the die paddle. The ground plane includes a gap where the transmission line extends to an edge of the packaged electronic device. In one embodiment, selected leads within the leadframe are configured with conductive connective structures as ground pins, source pins, and/or wave guides. In an alternate embodiment, a portion of the integrated antenna is embedded and partially exposed within the body of the packaged electronic device.

Abstract: In accordance with the present invention, there is provided a semiconductor package wherein a metal lid of the package is used as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to an internal die mounting pad of either a leadframe or an alternative type of substrate. Appropriate interconnect methods between the lid, the die pad, and the ground connections exterior to the semiconductor package include, but are not restricted to, conductive adhesives, wire bonding, bumps, tabs, or similar techniques.

Abstract: In one embodiment a semiconductor package includes a metal lid configured as a shield that effectively surrounds the active circuitry, and thus forms a type of Faraday shield. The lid is electrically coupled to a metalized area located on the surface of the active circuitry, or to an additional metalized die. Appropriate interconnect methods between the lid and the metalized die or metalized area include, but are not restricted to, wire bonding, bumps, tabs, or similar techniques.

Abstract: There is disclosed an integrated circuit (IC) package or semiconductor package including integrated spark or arc gaps which are uniquely configured to reduce the susceptibility of the package to being damaged from an electrostatic discharge (ESD) event. In an exemplary embodiment, each arc gap is collectively defined by an arc gap extension integrally connected to and protruding from the die pad of the package, and a corresponding lead thereof.

Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Abstract: A circuit device is placed within an opening of a conductive layer which is then partially encapsulated with an encapsulant so that the active surface of the circuit device is coplanar with the conductive layer. At least a portion of the conductive layer may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device may be placed on a conductive layer such that an active surface of circuit device is between conductive layer and an opposite surface of circuit device. The conductive layer has at least one opening to expose the active surface of circuit device. The encapsulant may be electrically conductive or electrically non-conductive.

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive or electrically non-conductive.

Abstract: A circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). At least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). Additionally, a circuit device (115) may be placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). The conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126,326) may be electrically conductive or electrically non-conductive.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.

Abstract: In one embodiment, circuit device (15) is placed within an opening of a conductive layer (10) which is then partially encapsulated with an encapsulant (24) so that the active surface of the circuit device (15) is coplanar with the conductive layer (10). In this embodiment, at least a portion of the conductive layer (10) may be used as a reference voltage plane (e.g. a ground plane). In one embodiment, circuit device (115) is placed on a conductive layer (100) such that an active surface of circuit device (115) is between conductive layer (100) and an opposite surface of circuit device (115). In this embodiment, conductive layer (100) has at least one opening (128) to expose the active surface of circuit device (115). The encapsulant (24, 126, 326) may be electrically conductive for some embodiments, and electrically non-conductive for other embodiments.