Abstract: Strings of solar cells having laser assisted metallization conductive contact structures, and their methods of manufacture, are described. For example, a solar cell string includes a first solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a first metal foil to the back side of the first solar cell. The solar cell string also includes a second solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a second metal foil to the back side of the second solar cell. The solar cell string also includes a conductive interconnect coupling the first and second solar cells, the conductive interconnect including a strain relief feature.

Abstract: Strings of solar cells having laser assisted metallization conductive contact structures, and their methods of manufacture, are described. For example, a solar cell string includes a first solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a first metal foil to the back side of the first solar cell. The solar cell string also includes a second solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a second metal foil to the back side of the second solar cell. The solar cell string also includes a conductive interconnect coupling the first and second solar cells, the conductive interconnect including a strain relief feature.

Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.

Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.

Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.

Abstract: Strings of solar cells having laser assisted metallization conductive contact structures, and their methods of manufacture, are described. For example, a solar cell string includes a first solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a first metal foil to the back side of the first solar cell. The solar cell string also includes a second solar cell having a front side and a back side, and one or more laser assisted metallization conductive contact structures electrically connecting a second metal foil to the back side of the second solar cell. The solar cell string also includes a conductive interconnect coupling the first and second solar cells, the conductive interconnect including a strain relief feature.

Abstract: Metallization of semiconductor substrates using a laser beam, and the resulting structures, e.g., micro-electronic devices, semiconductor substrates and/or solar cells, solar cell circuit, solar cell strings, and solar cell arrays are described. A solar cell string can include a plurality of solar cells. The plurality of solar cells can include a substrate and a plurality of semiconductor regions disposed in or above the substrate. A plurality of conductive contact structures is electrically connected to the plurality semiconductor regions. Each conductive contact structure includes a locally deposited metal portion disposed in contact with a corresponding one of the semiconductor regions.

Abstract: There is disclosed a garment closure comprising a front component, a rear component and an intermediate connector component. The connector component fastens the front component and the rear component together so that the front component and rear component are in spaced relationship relative to each other. The rear component is configured for insertion through a fastener aperture.

Abstract: There is disclosed a garment closure comprising a front component, a rear component and an intermediate connector component. The connector component fastens the front component and the rear component together so that the front component and rear component are in spaced relationship relative to each other. The rear component is configured for insertion through a fastener aperture.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: The present invention provides an apparatus for vertically interconnecting semiconductor die, integrated circuit die, or multiple die segments. Metal rerouting interconnects which extend to one or more sides of the die or segment can be optionally added to the die or multi die segment to provide edge bonding pads upon the surface of the die for external electrical connection points. After the metal rerouting interconnect has been added to the die on the wafer, the wafer is optionally thinned and each die or multiple die segment is singulated from the wafer by cutting or other appropriate singulation method. After the die or multiple die segments are singulated or cut from the wafer, insulation is applied to all surfaces of the die or multiple die segments, openings are made in the insulation above the desired electrical connection pads, and the die or multiple die segments are placed on top of one another to form a stack.

Abstract: Semiconductor die are typically manufactured as a large group of integrated circuit die imaged through photolithographic means on a semiconductor wafer or slice made of silicon. After manufacture, the silicon wafer is thinned, usually by mechanical means, and the wafer is cut, usually with a diamond saw, to singulate the individual die. The resulting individual integrated circuit has six exposed surfaces. The top surface of the die includes the circuitry images and any passivation layers that have been added to the top layer during wafer fabrication. The present invention describes a method for protecting and insulating all six surfaces of the die to reduce breakage, provide electrical insulation for these layers, and to provide physical surfaces that can be used for bonding one semiconductor die to another for the purpose of stacking die in an interconnected module or component.