Abstract: In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to the data memory. A connection identifier (ID), received in association with the access request; may include a buffer ID designating a buffer in the data memory in which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into the real address of the data memory, and accessing the data memory at a location corresponding to the real address. Different types of buffers, such as point-to-point, scatter, and gather buffers may be used, and different patterns, such as first-in-first out (FIFO), nested loop, matrix transforms may be used.

Abstract: An apparatus and a method for load balancing across multiple routes using an indirection table and hash function during a process of packet classification are disclosed. A network device such as a router includes a memory, a hash component, and a result memory. The memory is referred to as an indirection random access memory (“RAM”), is capable of storing information regarding number of paths from source devices to destination devices. The memory, in one embodiment, provides a base index value and a range number indicating the number of paths associated with the base index value. The hash component generates a hash index in response to the base index value and the range number. Upon generation of hash index, the result memory identifies a classification result in response to the hash index.

Abstract: In an embodiment, a model may be created using a register-transfer level (RTL) representation (or other cycle-accurate representation) of the controller and the circuitry in the communication fabric to the controller. The request sources may be replaced by transactors, which may generate transactions to test the performance of the fabric and controller. Accordingly, only the designs of the controller and the fabric circuitry may be needed to model performance in this embodiment. In an embodiment, at least some of the transactors may be behavioral transactors that attempt to mimic the operation of corresponding request sources. Other transactors may be statistical distributions, in some embodiments. In an embodiment, the transactors may include a transaction generator (e.g. behavioral or statistical) and a protocol translator configured to convert generated transactions to the communication protocol in use at the point that the transactor is connected to the fabric.

Abstract: An apparatus and method for using a direct memory access (“DMA”) to facilitate netflow statistics are disclosed. A network device such as a router or a switch, in one embodiment, includes a statistic component, a local memory, and a memory access controller. The statistic component is configured to gather information relating to net usage from packet flows or netflows in response to corresponding index values or tags. While the local memory such as a cache provides the index values or tags assignable to packet flows, the memory access controller such as a DMA transfers at least a portion of the index values or tags between the local memory and a main memory for enhancing capacity of the local memory.

Abstract: An apparatus for transferring data between buffers within a data processing architecture includes first and second memory devices. The apparatus further includes a first connection manager associated with a first buffer in the first memory device, and a second connection manager associated with a second buffer in the second memory device. The first and second connection managers manage data transfers between the first and second buffers. The first connection manager is configured to receive a token from the second connection manager in order to trigger data transfer between the first buffer and the second buffer. The first connection manager is further configured to initiate a data transfer between the first and second buffers in response to receiving the token. This token-based method for initiating data transfers between the connection managers requires little or no CPU intervention.

Abstract: A method includes providing a processor configured to execute instructions. The method may further include providing a first set of registers in the processor to store first data and first instructions associated with a first thread, and providing a second set of registers in the processor to store second data and second instructions associated with a second thread. The method may further include transmitting the first data and first instructions associated with the first thread to the first set of registers, and executing the first instructions in order to process the first data. The method may further include transmitting the second data and second instructions to the second set of registers while executing the first instructions and processing the first data. A corresponding apparatus is also disclosed and claimed herein.

Abstract: An apparatus for processing data may include an array of processing elements (such as an n×m or n×n array of processing elements) configured to simultaneously perform operations on a plurality of data elements using a single instruction. Each processing element in the array may be configured to transfer data directly to at least one neighboring processing element within the array. In selected embodiments, the apparatus may include exchange registers to temporarily store data transferred between neighboring processing elements.

Abstract: An apparatus, system, and method in accordance with the invention may include providing a multi-dimensional data structure and providing an address generation unit configured to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate the real addresses by executing a series of nested loops pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. The address generation unit may receive as inputs a set of parameters defining the characteristics of the nested loops. The method may then include accessing the data structure at the real addresses calculated by the address generation unit.

Abstract: A system in accordance with the invention may include a data memory storing a multi-dimensional (e.g., a two-dimensional) data structure. An address generation unit is provided to calculate real addresses in order to access the multi-dimensional data structure in a desired pattern. The address generation unit may be configured to calculate real addresses by moving across the multi-dimensional data structure between pairs of end points. The pairs of end points (as well as parameters such as the step size between the end points) may be pre-programmed into the address generation unit prior to accessing the multi-dimensional data structure. A processor, such as a vector processor, may be configured to access (e.g., read or write data to) the data structure at the real addresses calculated by the address generation unit.

Abstract: A system and method for generating a real address in data memory in response to a read/write request may include generating an access request to at least one of read and write data to a data memory. A connection ID may be received in association with the access request. This connection ID may include a buffer ID designating a buffer in data memory to which to access the data, and a port ID designating a pattern in which to access the data in the buffer. The method may further include translating the connection ID into a real address of the data memory, and accessing the data in the data memory at a location corresponding to the real address.

Abstract: Distributing packets from an input link to multiple output links involves categorizing each incoming packet, selecting a mapping algorithm based on the packet category, and using the selected mapping algorithm for each packet to determine an output link for the respective packet. If packets are from a category that requires the order of the packets to be maintained, then the selected mapping algorithm causes packets from the same set of packets to be distributed to the same output link. If packets are from a category that does not require the order of the packets to be maintained, then the selected mapping algorithm can cause packets to be distributed more evenly among the multiple output links. Hashing can be used to distribute in-order packets from the same set to the same output link. Load balancing and round-robin distribution can be used to distribute out-of-order packets more evenly across the output links.

Abstract: Managing packets in a shared memory buffer involves linking buffered packets into a linked list in the order that the packets are written into the shared memory buffer, examining the packets in the order of the linked list to determine which packets are intended for available output links, and then dispatching the oldest packet that is intended for an available output link even if the packet is preceded on the linked list by packets that are older but are intended for unavailable output links. Packets are stored with NEXT pointers that establish the linked list and output link identifiers that identify the intended output links of the packets. The head of the linked list is identified by a linked list HEAD pointer. When a packet is dispatched, the packet is removed from the linked list by adjusting the linked list HEAD pointer or the NEXT pointer of the previous packet.

Abstract: Distributing packets from an input link to multiple output links involves categorizing each incoming packet, selecting a mapping algorithm based on the packet category, and using the selected mapping algorithm for each packet to determine an output link for the respective packet. If packets are from a category that requires the order of the packets to be maintained, then the selected mapping algorithm causes packets from the same set of packets to be distributed to the same output link. If packets are from a category that does not require the order of the packets to be maintained, then the selected mapping algorithm can cause packets to be distributed more evenly among the multiple output links. Hashing can be used to distribute in-order packets from the same set to the same output link. Load balancing and round-robin distribution can be used to distribute out-of-order packets more evenly across the output links.

Abstract: Managing packets in a shared memory buffer involves linking buffered packets into a linked list in the order that the packets are written into the shared memory buffer, examining the packets in the order of the linked list to determine which packets are intended for available output links, and then dispatching the oldest packet that is intended for an available output link even if the packet is preceded on the linked list by packets that are older but are intended for unavailable output links. Packets are stored with NEXT pointers that establish the linked list and output link identifiers that identify the intended output links of the packets. The head of the linked list is identified by a linked list HEAD pointer. When a packet is dispatched, the packet is removed from the linked list by adjusting the linked list HEAD pointer or the NEXT pointer of the previous packet.