Abstract: An image sensor die may include a pixel array formed in an image sensor substrate and covered by a transparent cover layer. The transparent cover layer may be attached to the image sensor substrate using adhesive. Electrical interconnect structures such as conductive vias may be formed in the transparent cover layer and may be used in conveying electrical signals between the image sensor and a printed circuit board. The conductive vias may have one end coupled to a bond pad on the upper surface of the transparent cover layer and an opposing end coupled to a bond pad on the upper surface of the image sensor substrate. The conductive vias may pass through openings that extend through the transparent cover layer and the adhesive. Conductive structures such as wire bonds, stud bumps, or solder balls may be coupled to the bond pads on the surface of the transparent cover layer.

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract: Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer.

Abstract: Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer.

Abstract: An image sensor unit may have a backside-illuminated imager and an image co-processor stacked together. The image co-processor may be mounted in a cavity in a permanent carrier. The permanent carrier may include fluid channels that allow cooling fluid to flow past the image co-process and past the imager, thereby removing excess heat generated by the image sensor unit during operation.

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract: A method of fabricating semiconductor structures comprising sub-resolution alignment marks is disclosed. The method comprises forming a dielectric material on a substrate and forming at least one sub-resolution alignment mark extending partially into the dielectric material. At least one opening is formed in the dielectric material. Semiconductor structures comprising the sub-resolution alignment marks are also disclosed.

Abstract: An image sensor may be provided with an array of imaging pixels. A color filter array may be formed over photosensitive elements in the pixel array. The color filter array may include a Bayer color filter array. Separating material may be interposed between color filter elements of adjacent imaging pixels. The separating material may be relatively low index of refraction material configured to reduce or eliminate optical crosstalk between adjacent imaging pixels. The separating material may be air so that neighboring color filter elements are separated by an air gap. The air gaps may be formed during the color filter array fabrication process by depositing a sacrificial layer on the substrate, forming openings in the sacrificial layer, forming color filter elements in the openings, and removing remaining portions of the sacrificial layer that are formed between the color filter elements.

Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with terminals of the dies. The first opening separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening. In several embodiments, the method may include constructing an electrically conductive interconnect in at least a portion of the second opening and in electrical contact with the terminal.

Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

Abstract: Methods for forming interconnects in microelectronic workpieces and microelectronic workpieces formed using such methods are disclosed herein. One embodiment, for example, is directed to a method of processing a microelectronic workpiece including a semiconductor substrate having a plurality of microelectronic dies. The individual dies include integrated circuitry and a terminal electrically coupled to the integrated circuitry. The method can include forming a first opening in the substrate from a back side of the substrate toward a front side and in alignment with the terminal. The first opening has a generally annular cross-sectional profile and separates an island of substrate material from the substrate. The method can also include depositing an insulating material into at least a portion of the first opening, and then removing the island of substrate material to form a second opening aligned with at least a portion of the terminal.

Abstract: An imaging system may include an image sensor configured to image materials at near field imaging ranges from the image sensor. Near field imaging ranges may be on the scale of 1-10 pixel sizes from the image sensor. The materials being imaged may be fluorescent materials that emit radiation at fluorescent wavelengths when the materials are exposed to radiation at excitation wavelengths. The image sensor may include color filter materials that block radiation at excitation wavelengths while transmitting radiation at fluorescent wavelengths. The image sensor may include light guides that reduce cross-talk between pixels and improve localization of emitted radiation, thereby allowing the image sensor to determine which pixel(s) is (are) located beneath the materials being imaged. The light guides may include may include sloped sidewalls and may include reflective sidewalls, which may improve radiation collection (e.g., efficiency) and localization of emitted radiation.

Abstract: Methods for forming backside illuminated (BSI) image sensors having metal redistribution layers (RDL) and solder bumps for high performance connection to external circuitry are provided. In one embodiment, a BSI image sensor with RDL and solder bumps may be formed using a temporary carrier during manufacture that is removed prior to completion of the BSI image sensor. In another embodiment, a BSI image sensor with RDL and solder bumps may be formed using a permanent carrier during manufacture that partially remains in the completed BSI image sensor. A BSI image sensor may be formed before formation of a redistribution layer on the front side of the BSI image sensor. A redistribution layer may, alternatively, be formed on the front side of an image wafer before formation of BSI components such as microlenses and color filters on the back side of the image wafer.

Abstract: An image sensor unit has stacked imager and processor integrated circuits. The imager may have an image sensor pixel array on its front surface. Processor die may be mounted back-to-back with respective imagers on a wafer. A photodefinable dielectric film may cover the rear surface of the wafer. Metal traces in the photodefinable dielectric and through-silicon vias in each imager may be used to interconnect the processing circuitry on the front surface of a processor to the image sensor pixel array on the front surface of the imager. Openings may be formed in the photo definable dielectric to allow solder balls to form electrical connections with the metal traces. A cavity may be formed in a photo definable dielectric layer or an imager to accommodate the processor. The processor may also be mounted in a cavity in a separate silicon standoff structure before attaching the standoff structure to the imager.

Abstract: An imaging system may include an imager with frontside components such as imaging pixels and backside components. The backside components may include at least a first redistribution layer having metal trenches and through-silicon vias (TSVs) that couple at least some of the backside components to the frontside components. The metal trenches and through-silicon vias may be formed simultaneously. The through-silicon vias may have a width greater than the width of the metal trenches. The greater width of the through-silicon vias may facilitate forming the through-silicon vias simultaneously with the metal trenches.

Abstract: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.

Abstract: Several embodiments for semiconductor devices and methods for forming semiconductor devices are disclosed herein. One embodiment is directed to a method for manufacturing a microelectronic imager having a die including an image sensor, an integrated circuit electrically coupled to the image sensor, and electrical connectors electrically coupled to the integrated circuit. The method can comprise covering the electrical connectors with a radiation blocking layer and forming apertures aligned with the electrical connectors through a layer of photo-resist on the radiation blocking layer. The radiation blocking layer is not photoreactive such that it cannot be patterned using radiation. The method further includes etching openings in the radiation blocking layer through the apertures of the photo-resist layer.

Abstract: Conductive interconnect structures and formation methods using supercritical fluids are disclosed. A method in accordance with one embodiment of the invention includes forming a via in a substrate, with the via having a width and a length generally transverse to the width, and with a length being approximately 100 microns or more. The method can further include disposing a conductive material in the via while the via is exposed to a supercritical fluid. For example, copper can be disposed in the via by introducing a copper-containing precursor into the supercritical fluid and precipitating the copper from the supercritical fluid. Interconnect structures can be formed using this technique in a single generally continuous process, and can produce conductive structures having a generally uniform grain structure across the width of the via.

Abstract: A wafer of integrated circuits may be bonded to a carrier wafer using a layer of bonding material. The thickness of the wafer of integrated circuits may then be reduced using a series of grinding operations. After grinding, backside processing operations may be performed to form scribe channels that separate the die from each other and to form through-wafer vias. The scribe channels may be formed by dry etching and may have rectangular shapes, circular shapes, or other shapes. A pick and place tool may have a heated head. The bonding layer material may be based on a thermoplastic or other material that can be released by application of heat by the heated head of the pick and place tool. The pick and place tool may individually debond each of the integrated circuits from the carrier wafer and may mount the debonded circuits in packages.