Patents by Inventor Marcel Mitran

Marcel Mitran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8301434
    Abstract: A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.
    Type: Grant
    Filed: September 18, 2009
    Date of Patent: October 30, 2012
    Assignee: International Buisness Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Patent number: 8250557
    Abstract: There is disclosed a method and system for configuring a data dependency graph (DDG) to handle instruction scheduling in computer architectures permitting dynamic by-pass execution, and for performing dynamic by-pass scheduling utilizing such a configured DDG. In accordance with an embodiment of the invention, a heuristic function is used to obtain a ranking of nodes in the DDG after setting delays at all identified by-pass pairs of nodes in the DDG to 0. From among a list of identified by-pass pairs of nodes, a node that is identified as being the least important to schedule early is marked as “bonded” to its successor, and the corresponding delay for that identified node is set to 0. Node rankings are re-computed and the bonded by-pass pair of nodes are scheduled in consecutive execution cycles with a delay of 0 to increase the likelihood that a by-pass can be successfully taken during run-time execution.
    Type: Grant
    Filed: May 7, 2008
    Date of Patent: August 21, 2012
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Alexander Vasilevskiy
  • Publication number: 20120197854
    Abstract: A method for finding sequential patterns of attributes in a directed graph includes constructing a directed graph comprising multiple nodes and edges between the nodes. Each of the nodes may be assigned one or more attributes. Similarly, each of the edges may be assigned a weight value which may indicate the probably the edge will be traversed during traversal of the directed graph. The method may further include finding sequences of attributes in the directed graph that have some minimum amount of frequency and/or time support. In performing this step, the frequency support of each individual instance of a sequence of attributes may be calculated by multiplying the weight values along the edge or edges of the instance. A corresponding apparatus and computer program product are also disclosed and claimed herein.
    Type: Application
    Filed: March 27, 2012
    Publication date: August 2, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jose Nelson Amaral, Adam Paul Jocksch, Marcel Mitran
  • Publication number: 20120167067
    Abstract: A batching mechanism is provided that batches multiple Java Native Interface calls together such that the batch crosses the Java Native Interface boundary in a single transition. The batching mechanism operates by identifying a sequence of Java Native Interface calls to be made by native code, by encapsulating the identified sequence of Java Native Interface calls into a batch, and by communicating the batch as a single transition across the Java Native Interface boundary. In this manner, each call of the batch is encapsulated by iteratively performing for each call to be made, processes including identifying the Java Native Interface function to call, identifying the arguments to pass into the Java Native Interface function, dispatching to the Java Native Interface function and capturing the return value.
    Type: Application
    Filed: December 23, 2010
    Publication date: June 28, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Andrew R. Low, Marcel Mitran, Kishor V. Patil, Gavin Rolleston, Ivan Sham, Karl M. Taylor
  • Publication number: 20120117553
    Abstract: An enhanced function-descriptor-based dispatch in a multi-linkage environment receives user code containing a function compiled in a supplementary linkage convention of a caller to form an invoked function and determines whether the supplementary linkage convention of the caller for the invoked function matches a supplementary linkage implementation provided by a library. Responsive to a determination that the supplementary linkage convention of the caller for the invoked function matches a supplementary linkage implementation provided by the library, an embodiment selects the supplementary linkage implementation provided by the library and dispatches the invoked function in the selected supplementary linkage implementation provided by the library.
    Type: Application
    Filed: October 8, 2011
    Publication date: May 10, 2012
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Allan H. Kielstra, Andrew R. Low, Marcel Mitran, Kishor V. Patil, Ivan K. Y. Sham
  • Publication number: 20110314260
    Abstract: A computer employs a set of General Purpose Registers (GPRs). Each GPR comprises a plurality of portions. Programs such as an Operating System and Applications operating in a Large GPR mode, access the full GPR, however programs such as Applications operating in Small GPR mode, only have access to a portion at a time. Instruction Opcodes, in Small GPR mode, may determine which portion is accessed.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Marcel Mitran, Timothy J. Slegel
  • Publication number: 20110314263
    Abstract: An arithmetic/logical instruction is executed having interlocked memory operands. when executed obtains a second operand from a location in memory, and saves a temporary copy of the second operand, the execution performs an arithmetic or logical operation based on the second operand and a third operand and stores the result in the memory location of the second operand, and subsequently stores the temporary copy in a first register.
    Type: Application
    Filed: June 22, 2010
    Publication date: December 22, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dan F. Greiner, Marcel Mitran, Timothy J. Slegel
  • Patent number: 8042100
    Abstract: Systems, methods, and computer products for evaluating robustness of a list scheduling framework. Exemplary embodiments include a method for evaluating the robustness of a list scheduling framework, the method including identifying a set of compiler benchmarks known to be sensitive to an instruction scheduler, running the set of benchmarks against a heuristic under test, H and collect an execution time Exec(H[G]), where G is a directed a-cyclical graph, running the set of benchmarks against a plurality of random heuristics Hrand[G]i, and collect a plurality of respective execution times Exec(Hrand[G])i, computing a robustness of the list scheduling framework, and checking robustness check it against a pre-determined threshold.
    Type: Grant
    Filed: August 27, 2007
    Date of Patent: October 18, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Joran S. C. Siu, Alexander Vasilevskiy
  • Publication number: 20110202748
    Abstract: A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Christian Jacobi, Marcel Mitran, Timothy J. Slegel, Charles F. Webb
  • Publication number: 20110202729
    Abstract: A disjoint instruction for accessing operands in memory while executing in a processor of a plurality of processes interrogates a state indicator settable by other processors to determine if the disjoint instruction accessed the operands without an intervening store operation from another processor to the operand. A condition code is set based on the state indicator.
    Type: Application
    Filed: February 18, 2010
    Publication date: August 18, 2011
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran
  • Publication number: 20110107068
    Abstract: One embodiment of a method for eliminating redundant operations establishing common properties includes identifying a first virtual register storing a first value having a common property. The method may assign the first virtual register to use a real register. The method may further identify a second virtual register storing a second value also having the common property. The method may assign the second virtual register to use the same real register after the first value is no longer live. As a result of assigning the second virtual register to the first real register, the method may eliminate an operation configured to establish the common property for the second virtual register since this operation is redundant and is no longer needed.
    Type: Application
    Filed: October 26, 2010
    Publication date: May 5, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: MARCEL MITRAN, KISHOR V. PATIL, JORAN S. C. SIU, MARK G. STOODLEY, VIJAY SUNDARESAN
  • Patent number: 7937552
    Abstract: Illustrative embodiments provide a computer implemented method, an apparatus in the form of a data processing system and a computer program product for cache line reservations. In one embodiment, the computer implemented method comprises, dividing a memory into an unreserved section and a set of reserved sections. The method performs selected allocations of the memory only from the set of reserved sections, and performing un-selected allocations of the memory from the unreserved section. The method further mapping a specified selected allocation of the memory to a same corresponding line of cache memory each time the mapping for the specified selected allocation of the memory occurs, thereby maintaining locality.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: May 3, 2011
    Assignee: International Business Machines Corporation
    Inventors: Daryl James Maier, Marcel Mitran, Vijay Sundaresan
  • Patent number: 7930686
    Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Ali L. Sheikh
  • Publication number: 20110071813
    Abstract: Dynamic creation of a spatially aware emulation environment comprising Host cells of Host pages corresponding to Guest cells of Guest pages of Guest instructions. Each Host cell comprises a semantic routine for emulating a corresponding Guest instruction located at the corresponding Guest cell of the guest page.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Publication number: 20110071815
    Abstract: A instructions of a Guest program to be emulated by a Host computer occupy one or more Guest cells of Guest memory, each Guest cell having a corresponding Host cell in Host memory. The emulator selects a Host cell for emulating a Guest instruction. When the Host cell corresponds to a Guest cell other than a cell aligned with the beginning of the Guest instruction, a wild branch handling routine is executed.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Publication number: 20110071816
    Abstract: A selected group of Guest machine instructions in an emulation environment are translated to a semantic routine of Host machine instructions, wherein Guest cells corresponding to an opcode portion of a Guest instruction are mapped to corresponding Host cells, wherein the semantic routine of Host machine instructions are patched into a Host cell corresponding to the first Guest cell of the group of Guest machine instructions, wherein other Host cells of the corresponding Host cells are patched with semantic routines for emulating single instructions associated with the corresponding Guest cell.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Publication number: 20110071814
    Abstract: A plurality of Guest cells of Guest instructions are provided with corresponding Host cells for emulating Guest instructions, each Guest instruction having a Guest cell corresponding to a Host cell. Each of the Host cells are initialized with an initialization routine for discovering a corresponding semantic routine for emulating the Guest instruction.
    Type: Application
    Filed: September 18, 2009
    Publication date: March 24, 2011
    Applicant: International Business Machines Corporation
    Inventors: Theodore J. Bohizic, Reid T. Copeland, Marcel Mitran, Ali I. Sheikh
  • Patent number: 7908596
    Abstract: Automatic inspection of compiled code. In response to revising a compiler, the functionality of that compiler is verified. Specific code is compiled using a first version of the compiler, as well as a second version of the compiler. Each compiled code is then applied to machine state to obtain multiple machine states. The machine states are then compared to determine if they are equal.
    Type: Grant
    Filed: January 5, 2007
    Date of Patent: March 15, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Alexander Vasilevskiy
  • Publication number: 20110054879
    Abstract: The illustrative embodiments provide a computer implemented method, apparatus, and computer program product for accelerating execution of a program, written in an object oriented programming language, in an emulated environment. In response to receiving a request for an accelerated communications session from a guest virtual machine in the emulated environment, a native virtual machine is initiated external to the emulated environment but within the computing device hosting the emulated environment. Thereafter, an accelerated communications link is established between the guest virtual machine and the native virtual machine. The accelerated communications link enables a transfer of managed code between the guest virtual machine and the native virtual machine. The managed code is then executed by the native virtual machine.
    Type: Application
    Filed: August 26, 2010
    Publication date: March 3, 2011
    Applicant: IBM Corporation
    Inventors: Francis Bogsanyl, Graeme Johnson, Andrew Low, Marcel Mitran, Ali Sheikh
  • Publication number: 20100251210
    Abstract: A method for finding sequential patterns of attributes in a directed graph includes constructing a directed graph comprising multiple nodes and edges between the nodes. Each of the nodes may be assigned one or more attributes. Similarly, each of the edges may be assigned a weight value which may indicate the probably the edge will be traversed during traversal of the directed graph. The method may further include finding sequences of attributes in the directed graph that have some minimum amount of frequency and/or time support. In performing this step, the frequency support of each individual instance of a sequence of attributes may be calculated by multiplying the weight values along the edge or edges of the instance. A corresponding apparatus and computer program product are also disclosed and claimed herein.
    Type: Application
    Filed: March 24, 2009
    Publication date: September 30, 2010
    Applicant: International Business Machines Corporation
    Inventors: Jose Nelson Amaral, Adam Paul Jocksch, Marcel Mitran