Abstract: The present disclosure is directed to an electroless plating process using a panel basket for holding semiconductor panels comprising a plurality of metal pads and shielding the metal pads from contaminants and over-etching and under-etching caused by the contaminants.

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes light-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.

Abstract: Embodiments herein relate to systems, apparatuses, and/or processes directed to a package or a manufacturing process flow for creating a package that uses multiple seeding techniques to fill vias in the package. Embodiments include a first layer of copper seeding coupled with a portion of the boundary surface and a second layer of copper seeding coupled with the boundary surface or the first layer of copper seeding, where the first layer of copper seeding and the second layer of copper seeding have a combined thickness along the boundary surface that is greater than a threshold value.

Abstract: An interconnection structure is disclosed. The interconnection structure includes a dielectric layer, an interfacial TiC layer on the dielectric layer, the interfacial TiC layer having a uniform thickness, and a Ti layer on the TiC layer.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, an electronic package comprises a package substrate, a first die over the package substrate, the first die having a first bump pitch, a second die over the package substrate, the second die having a second bump pitch that is greater than the first bump pitch, and a plurality of conductive traces over the package substrate, the plurality of conductive traces electrically coupling the first die to the second die. In an embodiment, a first end region of the plurality of conductive traces proximate to the first die has a first line space (L/S) dimension, and a second end region of the plurality of conductive traces proximate to the second die has a second L/S dimension. In an embodiment, the second L/S dimension is greater than the first L/S dimension.

Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a first layer of a package substrate and a conductive trace over the first layer of the package substrate. In an embodiment, the conductive trace comprises a conductive body with a first surface over the first layer of the package substrate, a second surface opposite the first surface, and sidewall surfaces coupling the first surface to the second surface. In an embodiment, the second surface has a first roughness and the sidewall surfaces have a second roughness that is less than the first roughness.

Abstract: Embodiments include package substrates and a method of forming the package substrates. A package substrate includes a self-assembled monolayer (SAM) layer over a first dielectric, where the SAM layer includes first end groups and second end groups. The second end groups may include a plurality of hydrophobic moieties. The package substrate also includes a conductive pad on the first dielectric, where the conductive pad has a bottom surface, a top surface, and a sidewall, and where the SAM layer surrounds and contacts a surface of the sidewall of the conductive pad. The hydrophobic moieties may include fluorinated moieties. The conductive pad includes a copper material, where the top surface of the conductive pad has a surface roughness that is approximately equal to a surface roughness of the as-plated copper material. The SAM layer may have a thickness that is approximately 0.1 nm to 20 nm.

Abstract: Embodiments of the present disclosure describe techniques for providing an apparatus with a substrate provided with plasma treatment. In some instances, the apparatus may include a substrate with a surface that comprises a metal layer to provide signal routing in the apparatus. The metal layer may be provided in response to a plasma treatment of the surface with a functional group containing a gas (e.g., nitrogen-based gas), to provide absorption of a transition metal catalyst into the surface, and subsequent electroless plating of the surface with a metal. The transition metal catalyst is to enhance electroless plating of the surface with the metal. Other embodiments may be described and/or claimed.

Abstract: Embodiments include a package substrate, a method of forming the package substrate, and a self-assembled monolayers (SAM) layer. The package substrate includes a SAM layer on portions of a conductive pad, where the SAM layer includes alight-reflective moieties. The package substrate also includes a via on a surface portion of the conductive pad, and a dielectric on and around the via, the SAM layer, and the conductive pad, where the SAM layer surrounds and contacts a surface of the via. The SAM layer may be an interfacial organic layer. The light-reflective moieties may include a hemicyanine, a cyclic-hemicyanine, an oligothiophene, and/or a conjugated aromatic compound. The SAM layer may include a molecular structure having a first end group of a first monolayer, an intermediate group, a fifth end group of a second monolayer, and one or more of a first and second light-reflective moieties.

Abstract: Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.

Abstract: Techniques and mechanisms for bonding structures of a circuit device with a monolayer. In an embodiment, a patterned metallization layer or a first dielectric layer includes a first surface portion. The first surface portion is exposed to first molecules which each include a first head group and a first end group which is substantially non-reactive with the first head group. The first head groups attach to the first portion to form a first self-assembled monolayer, which is subsequently reacted with second molecules to form a second monolayer comprising moieties of the first molecules. In another embodiment, the first head group comprises a first moiety comprising a sulfur atom or a nitrogen atom, where the first end group comprises one of an acid moiety, an acid anhydride moiety, an aliphatic alcohol moiety, an aromatic alcohol moiety, or an unsaturated hydrocarbon moiety.

Abstract: Described herein are devices and techniques for measuring a thickness of a surface layer. A device can include a detector, a processor, and a memory. The detector can be arranged to receive reflected light from a surface of a sample. The processor can be in electrical communication with the detector. The memory can store instructions that, when executed by the processor, can cause the processor to perform operations. The operations can include receiving optical data from the detector, determining a polarization change of the reflected light, the polarization change being a function of the optical data, and determining a thickness of the surface layer using the polarization change and the wavelength of the incident light. The optical data can include information regarding the phase difference of the reflected light and the incident light. Also described are other embodiments.

Abstract: A material thickness adjustment device and associated methods are shown. Material thickness adjustment devices and methods shown include eddy current measurement to determine material thickness during a deposition or removal operation. Feedback from the measured thickness may then be applied to adjust one or more processing parameters to meet a desired thickness.