Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

Abstract: A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

Abstract: A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.

Abstract: Techniques and corresponding circuitry are presented for the detection of wordline leakage in a memory array. In an exemplary embodiment, a capacitive voltage divider is used to translate the high voltage drop to low voltage drop that can be compared with a reference voltage to determine the voltage drop due to leakage. An on-chip self calibration method can help assure the accuracy of this technique for detecting leakage limit. In other embodiments, the current drawn by a reference array, where a high voltage is applied to the array with all wordlines non-selected, is compared to the current drawn by an array where the high voltage is applied and one or more selected wordlines. In these current based embodiments, the reference array can be a different array, or the same array as that one selected for testing.

Abstract: Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.

Abstract: A voltage regulator is disclosed. The voltage regulator has a voltage generation circuit that outputs a regulated voltage and a load current. The voltage regulation circuit has a sensing circuit that senses a peak magnitude of the load current and stores a peak signal that is based on the peak load current magnitude. The sensing circuit receives at least one signal that is input to the voltage regulation circuit and senses the peak magnitude of the load current. The voltage regulation circuit has a current generation circuit that generates a compensation current that has a magnitude that is proportional to the peak load current magnitude. The current generation circuit generates the compensation current based on the peak signal. The compensation current is provided during a time interval that is defined by at least one signal that is input to the voltage regulation circuit.

Abstract: Circuitry for performing a set or reset process for a reversible resistance-switching memory element in a memory device. A ramped voltage is applied to the memory cell and its state is constantly monitored so that the voltage can be discharged as soon as the set or reset process is completed, avoiding possible disturbs to the memory cell. One set circuit ramps the voltage using a current source, while detecting a current peak using an op-amp loop. One reset circuit ramps the voltage using an op-amp loop, while detecting a current peak by continuing to draw current at the peak current to maintain the output signal stable. Another set circuit ramps the voltage using an op-amp loop and a source-follower configuration. Another reset circuit ramps the voltage using an op-amp loop and a source-follower configuration with level shifting to reduce power consumption. Faster detection and shutoff, and stable operation, are achieved.

Abstract: A voltage regulator is disclosed. The voltage regulator has a voltage generation circuit that outputs a regulated voltage and a load current. The voltage regulation circuit has a sensing circuit that senses a peak magnitude of the load current and stores a peak signal that is based on the peak load current magnitude. The sensing circuit receives at least one signal that is input to the voltage regulation circuit and senses the peak magnitude of the load current. The voltage regulation circuit has a current generation circuit that generates a compensation current that has a magnitude that is proportional to the peak load current magnitude. The current generation circuit generates the compensation current based on the peak signal. The compensation current is provided during a time interval that is defined by at least one signal that is input to the voltage regulation circuit.

Abstract: A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

Abstract: A CMOS image sensor includes a plurality of pixels arranged column and rows in an array; a column circuit for storing reset values and a value after integration; a correlated double sampler which derives an image signal from the reset and the value after integration; and an anti-eclipse circuit physically separately from the column circuit and electrically connected to one or shared between multiple columns of pixels for restoring corrupted column voltage on a column of pixels.

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: The invention relates to a low supply voltage analog multiplier which comprises a pair of differential cells, each cell comprising a pair of bipolar transistors with coupled emitters. A first transistor of each cell receives an input signal on its base terminal and has its collector terminal coupled to a first voltage reference through a bias member. Advantageously, the second transistor of each cell is a diode configuration, and the cells are interconnected at a common node corresponding to the base terminals of the second transistors in each pair. This multiplier can be supplied very low voltages and still exhibit a high rate of operation along with reduced harmonic distortion of the output signal, even with input signals of peak-to-peak amplitude above 600 mV.

Abstract: A finite impulse response (FIR) filter for implementing a Hilbert transform is provided. The FIR filter includes a plurality of programmable delay cells connected in cascade between an input terminal of the FIR filter and an output terminal of the FIR filter. Each programmable delay cell has associated therewith a constant filter coefficient and a programmable delay coefficient. The FIR filter is also applicable for processing signals originated by the reading of data from a magnetic storage media which employs perpendicular recording.

Abstract: The invention relates to an elementary biquadratic cell for programmable time-continuous analog filters. The biquadratic cell is coupled between a first voltage reference and a second voltage reference and has at least one pair of input terminals and first and second pairs of output terminals. The cell includes a pair of half-cells, which half-cells are structurally identical with each other. Each half-cell comprises at least a first transistor coupled between the first and the second voltage reference and having a base terminal connected to a respective one of the input terminals. Each half-cell further comprises second and third transistors coupled between the first and second voltage references. The second transistor has a base terminal connected to the first output terminal of the first pair of output terminals and a collector terminal connected to the first output terminal of the second pair of output terminals.

Abstract: A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.