Charge pump system that dynamically selects number of active stages
A multi-stage charge pump selects the number of active stages dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used to drive the external load, while the slave section drives an adjustable internal load. The adjustable internal load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave section with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.
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This invention pertains generally to the field of charge pumps and more particularly to multi-stage charge pumps where the number of active stages is variable.
BACKGROUNDCharge pumps use a switching process to provide a DC output voltage larger or lower than its DC input voltage. In general, a charge pump will have a capacitor coupled to switches between an input and an output. During one clock half cycle, the charging half cycle, the capacitor couples in parallel to the input so as to charge up to the input voltage. During a second clock cycle, the transfer half cycle, the charged capacitor couples in series with the input voltage so as to provide an output voltage twice the level of the input voltage. This process is illustrated in
Charge pumps are used in many contexts. For example, they are used as peripheral circuits on flash and other non-volatile memories to generate many of the needed operating voltages, such as programming or erase voltages, from a lower power supply voltage. A number of charge pump designs, such as conventional Dickson-type pumps, are know in the art. But given the common reliance upon charge pumps, there is an on going need for improvements in pump design, particularly with respect to trying to reduce the amount of layout area and the efficiency of pumps.
SUMMARY OF THE INVENTIONAccording to a first set of aspects, a charge pump system includes a master charge pump section to provide an output voltage at an external output node. The master charge pump section includes first regulation circuitry and a first charge pump. The first regulation circuitry is connected to receive the output voltage and a reference voltage and supply an oscillator signal having a frequency determined from the output voltage and the reference voltage. The first charge pump is connected to receive the oscillator frequency of the first regulation circuitry and to generate the output voltage while operating according to the oscillator frequency of the first regulation circuitry. The first charge pump has a plurality of stages and the number of active stages is settable by a first control signal. The charge pump system also includes an internal load having an adjustable value. The system further includes a slave charge pump section connected to drive the internal load and that includes second regulation circuitry and a second charge pump. The second regulation circuitry is connected to receive the voltage driving the internal load and the reference voltage and to supply an oscillator signal having a frequency determined from the voltage driving the internal load and the reference voltage. The second charge pump is connected to receive the oscillator frequency of the second regulation circuitry and to generate the voltage driving the internal load while operating according to the oscillator frequency of the second regulation circuitry, wherein the second charge pump has the same number of stages as the first charge pump and the number of active stages is settable by a second control signal. Control logic on the charge pump system is connected to master charge pump section to receive the oscillator frequency of the first regulation circuitry and supply the first control signal, to the slave charge pump section to receive the oscillator frequency of the second regulation circuitry and supply the second control signal, and is also connected to the internal load to set its adjustable value. The control logic can set the value of the adjustable load based upon a comparison of the oscillator frequencies of the first and second regulation circuitry while the first and second charge pumps are operating with the same number of active stages, and can alter the number of active stages in the first charge pump based upon a comparison of the oscillator frequencies of the first and second regulation circuitry while the first and second charge pumps are operating with a different number of active stages.
According to another set of aspects, a method of operating a charge pump system to drive an external load. The method includes driving the external load using a master charge pump of a multi-stage, frequency regulated design. The number of stages active in the master charge pump is settable, and the master charge pump drives the load using a first number of active stages and a first regulated frequency. The method also includes driving an adjustable internal load using a slave charge pump of the same design as the master charge pump, where the slave charge pump is driving the adjustable load using the first number of active stages and a second regulated frequency. The system determines a level of the internal load based upon a comparison of the first and second regulated frequencies and drives the internal load set to the determined level using the slave charge pump with a second number of active stages, where the second number is different than the first number, and using a third regulated frequency. The system determines whether to change the number of active stages in the master charge pump based upon a comparison of the first and third regulated frequencies.
Various aspects, advantages, features and embodiments of the present invention are included in the following description of exemplary examples thereof, which description should be taken in conjunction with the accompanying drawings. All patents, patent applications, articles, other publications, documents and things referenced herein are hereby incorporated herein by this reference in their entirety for all purposes. To the extent of any inconsistency or conflict in the definition or use of terms between any of the incorporated publications, documents or things and the present application, those of the present application shall prevail.
The various aspects and features of the present invention may be better understood by examining the following figures, in which:
In order to maximize power efficiency for a generic regulated charge-pump across the full output voltage range and across power supply, temperature and process corner variations, the techniques presented in following present a multi-stage charge pump where the number of active stages is selected dynamically. In the exemplary embodiment, this is done by having a multi-stage master charge pump section in which the number of active stages is settable and a slave charge pump section that is of the same design as the master section. The master section is used drive the external load, while the slave section drives an adjustable internal load. The adjustable load is set by control logic by comparing the operation of the two sections. The control logic then operates the slave sections with a different number of active stages than the master stage in order to determine whether the master stage is using the optimal number of active stages. The control logic can then change the number of active stages accordingly.
Before discussing the exemplary embodiments, multi-stages charge pumps in general will be discussed some. A positive charge pump (CPP) 201, represented in
If the desired VOUT is not equal to the actual VOUT (such as 2N*VIN, where N is the number of stages, for the pump design of
For purposes of this exposition, when reference to a particular design is needed, the following discussion will use a 3-stage charge pump, where the individual stages are as shown in
Charge pumps find many applications in integrated circuit contexts where the system needs, in at least some phases of its operations, voltage values that extend beyond those available from the power supply. In particular, non-volatile memory devices often operate on fairly low supply voltage values, but require higher voltage levels for the writing and erasing of data. The techniques presented here can be advantageously used is such non-volatile memory devices, including the EEPROM based flash memory such as those described in U.S. Pat. Nos. 5,570,315, 5,903,495, 6,046,935 or the sort of “3D” structure presented in U.S. Pat. No. 7,696,812 and references found therein.
One commonly used figure of merit for a charge-pump circuit is the power efficiency ratio: η=(VOUT*IOUT)/(VIN*IIN), where VOUT=output voltage from the pump, IOUT=average current delivered by the pump to the load, IIN=average current delivered to the pump from VIN and VIN=lower reference voltage used to generate VOUT. The maximum value for η is one, but this is never achieved with real circuits due to the non ideal properties of CMOS devices. Plotting the power efficiency versus output voltage for a wide voltage range, the output curve would typically be something like that shown in
In the prior art, the pump configuration is usually chosen based only on the required maximum VOUT voltage and usually does not take into consideration factors such variation in temperature, VIN and process variations that affect the systems output. With such an approach and for VOUT close to the values where two adjacent efficiency curves intersect, the variation of process or external variable could make the selected configuration to no longer be the optimum one in term of efficiency. In the techniques presented in the following, extra circuitry is added to the conventional charge pump that continuously monitors the efficiency of the pump and modifies its configuration in order to pick for each VOUT voltage the correct number of stages to achieve the maximum efficiency available by the topology of the charge-pump stage.
An underlying idea that the exemplary embodiments exploit is related to the efficiency plots of
The frequency of operation is also affected by the number of stages being used in a charge pump.
The lower portion of
The one replica charge pump can output the same VOUT as the main pump, but delivers a current IDAC_CPP which need only be a fraction of the master pump's IOUT. The load 733 for the charge pump is adjustable and is here taken as a transistor whose gate is controlled by IDAC 735, represented as a having a sort of current mirror arrange driven by the adjusted current. The other elements of the slave section 721 are used to set the value of the load 733 to mimic the actual load being driven by the master stage 701, vary the active number of stages in the slave pump cells 723 while driving this load, determine whether it is more efficient to drive the load with the varied number of stages, and, if so, alter the number of active stages in the master pump.
A phase-frequency detection (PFD) circuit 739 is connected to receive and compare the frequencies of the master section's oscillator 709 and the slave section's VCO 729. The PFD 739 can receive the value of each of these frequencies or a fraction of them. As discussed in the following, for determining the load value of 733, the frequencies are compared directly, while for determining the number of stages to use, fractional parts of the frequencies are compared. In the exemplary embodiment, both of the frequencies can be reduced by a factor of 2 by the latches 745 and 747, where the respective outputs are fed to the multiplexers 741 and 734. Whether the frequency or its reduced value is passed by the multiplexers is then determined by the control logic 749. The result of the comparison by PFD 739 into the control logic block 749. The control logic circuit 749 controls the timing and the number of enabled stages for both MASTER_CPP 701 and SLAVE_CPP 721. The detail of the control logic is also based on the number of stages active at the time.
In order to dynamically determine the number of enabled stages for MASTER_CPP 701, there are exemplary embodiment alternated two modes of operation of the SLAVE_CPP section 721. In the “locking mode” (ILOCK_PHASE), the slave pump 723 and the master pump 703 have the same number of active stages. By having the 4 (in this example) bit UP/DOWN counter 737 change the value of IDAC_CPP, the system varies the load to achieve the state where both charge pumps have the same output voltage and operate at the same frequency. The input VILOCK is used when the system is not trying to regulate the load to stop changing the count and freeze the IDAC value. (If design of the slave section differed from that of that of the master section, the equalization of loads would typically be more involved.) Once the loads of the two sections are the same, then in the testing phase the slave section can be used to determine whether the number of active stages is the number that should be used for the specific load.
In the testing mode the load is fixed to the value reached during the locking phase. The control logic circuit 749 then increases or decreases by one the number of active stages in 723. The frequencies are then compared again by PFD 739. If the number of stages of in the slave pump 723 is decreased, and the new frequency of the slave section is higher than that half the frequency of the master pump, then the control logic 749 decreases also the number of active stages in the master pump cells 703. This comparison is made by the control logic switching the multiplexer 734 to feed the output of 747 into PFD 739. To see whether more active stages would be better, the number of active stages in 723 is increased by one and the slave frequency (fclk_SLAVE) is then compared with half the frequency of master value fclk_MASTER. If fclk_SLAVE<0.5*fclk_MASTER, the control logic increments by one the number of active stages of the master charge-pump. The comparison based on half frequencies used in the example is somewhat empirical and based on the specifics of the particular pump's design, but for the voltage double structure of
As the load on the master pump at VOUT can change, the load on the slave section needs be periodically adjusted to match and the number of active stages rechecked. The control logic circuit periodically alternates the two mode of operation as illustrated in the exemplary embodiment of
The result of the power efficiency for a pump system using this architecture is illustrate in
As noted above, the description above was based on a specific exemplary embodiment, but the techniques are more widely applicable to other multi-stage charge pump arrangement. The exemplary charge pump system of
As discussed above, the arrangement of
Although the invention has been described with reference to particular embodiments, the description is only an example of the invention's application and should not be taken as a limitation. Consequently, various adaptations and combinations of features of the embodiments disclosed are within the scope of the invention as encompassed by the following claims.
Claims
1. A charge pump system comprising:
- a master charge pump section to provide an output voltage at an external output node, including: first regulation circuitry connected to receive the output voltage and a reference voltage and supply an oscillator signal having a frequency determined from the output voltage and the reference voltage; and a first charge pump connected to receive the oscillator frequency of the first regulation circuitry and to generate the output voltage while operating according to the oscillator frequency of the first regulation circuitry, wherein the first charge pump has a plurality of stages and the number of active stages is settable by a first control signal;
- an internal load having an adjustable value;
- a slave charge pump section connected to drive the internal load, including: second regulation circuitry connected to receive a voltage driving the internal load and the reference voltage and supply another oscillator signal having a frequency determined from the voltage driving the internal load and the reference voltage; and a second charge pump connected to receive the other oscillator frequency of the second regulation circuitry and to generate the voltage driving the internal load while operating according to the oscillator frequency of the second regulation circuitry, wherein the second charge pump has the same number of stages as the first charge pump and the number of active stages is settable by a second control signal; and
- control logic connected to the master charge pump section to receive the oscillator frequency of the first regulation circuitry and supply the first control signal, connected to the slave charge pump section to receive the other oscillator frequency of the second regulation circuitry and supply the second control signal, and connected to the internal load to set the adjustable value thereof,
- wherein the control logic can set the adjustable value of the internal load based upon a comparison of the oscillator frequencies of the first and second regulation circuitries while the first and second charge pumps are operating with the same number of active stages, and can alter the number of active stages in the first charge pump based upon a comparison of the oscillator frequencies of the first and second regulation circuitries while the first and second charge pumps are operating with a different number of active stages.
2. The charge pump system of claim 1, wherein the first and second regulation circuitries each include:
- a comparator having a first input connected to receive the reference voltage and a second input connected, for the first regulation circuitry, to receive a voltage derived from the output voltage and, for the second regulation circuitry, a voltage derived from the voltage driving the internal load, and
- an oscillator controlled by the output of the comparator to provide the oscillator frequency.
3. The charge pump system of claim 1, wherein the internal load includes a transistor connected between the output of the second charge pump and ground and having a gate voltage controlled by the control logic.
4. The charge pump system of claim 1, where the first and second charge pumps each have N stages, where N is an integer greater than 1, and the number of active stages in the first and second charge pumps is settable from 1 to N by the first and second control signals, respectively.
5. The charge pump system of claim 1, wherein when connected to drive an external load with the output voltage, the control logic alternately performs determinations of whether to adjust the internal load and of whether to alter the number of active stages in the first charge pump.
6. The charge pump system of claim 5, wherein the determinations of whether to alter the number of active stages includes determinations both of whether to increase and of whether to decrease the number of active stages in the first charge pump.
7. The charge pump system of claim 6, wherein the determinations of whether to alter the number of active stages further includes a repeating sequence of two determinations of whether to increase the number of active stages in the first charge pump and one determination of whether to decrease the number of active stages in the first charge pump.
8. The charge pump system of claim 1, wherein the control logic includes a frequency comparator circuit connected, when setting the value of the internal load, to receive the frequencies of the first and second regulation circuitries, where the control logic increases the value of the internal load when the frequency of the first regulation circuitry is higher than the frequency of the second regulation circuitry and decreases the value of the internal load when the frequency of the first regulation circuitry is lower than the frequency of the second regulation circuitry.
9. The charge pump system of claim 1, wherein the control logic includes a frequency comparator circuit connected, when determining whether to increase the number active stages in the first charge pump, to receive the frequency of the second regulation circuitry and a predetermined fraction that is less than one of the frequency of the first regulation circuitry while operating the second charge pump with one more active stage than the first charge pump.
10. The charge pump system of claim 1, wherein the control logic includes a frequency comparator circuit connected, when determining whether to decrease the number active stages in the first charge pump, to receive the frequency of the first regulation circuitry and a predetermined fraction that is less than one of the frequency of the second regulation circuitry while operating the second charge pump with one fewer active stage than the first charge pump.
11. A method of operating a charge pump system to drive an external load, comprising:
- driving the external load using a master charge pump of a multi-stage, frequency regulated design, wherein the number of stages active is settable, and the master charge pump is driving the external load using a first number of active stages and a first regulated frequency;
- driving an adjustable internal load using a slave charge pump of the same design as the master charge pump, wherein the slave charge pump is driving the adjustable internal load using the first number of active stages and a second regulated frequency;
- determining a level of, the adjustable internal load based upon a comparison of the first and second regulated frequencies;
- driving the adjustable internal load set to the determined level using the slave charge pump with a second number of active stages, wherein the second number is different than the first number, and using a third regulated frequency; and
- determining whether to change the number of active stages in the master charge pump based upon a comparison of the first and third regulated frequencies.
12. The method of claim 11, wherein the second number of stages is one greater than the first number of stages.
13. The method of claim 12, wherein determining whether to change the number of active stages in the master charge pump includes:
- determining whether the third regulated frequency is greater than a predetermined fraction of the first regulated frequency, the predetermined fraction being between one and zero;
- in response to determining that the third regulated frequency is greater than the predetermined fraction of the first regulated frequency, continuing to operate the master charge pump with the first number of active stages; and
- in response to determining that the third regulated frequency is not greater than the predetermined fraction of the first regulated frequency, subsequently operating the master charge pump with the second number of active stages.
14. The method of claim 13, wherein the predetermined fraction is one half.
15. The method of claim 11, wherein the second number of stages is one less than the first number of stages.
16. The method of claim 15, wherein determining whether to change the number of active stages in the master charge pump includes:
- determining whether the first regulated frequency is greater than a predetermined fraction of the third regulated frequency, the predetermined fraction being between one and zero;
- in response to determining that the first regulated frequency is greater than the predetermined fraction of the third frequency, subsequently operating the master charge pump with the second number of active stages; and
- in response to determining that the first regulated frequency is not greater than the predetermined fraction of the third regulated frequency, continuing to operate the master charge pump with the first number of active stages.
17. The method of claim 16, wherein the predetermined fraction is one half.
18. The method of claim 11, wherein determining the level of the adjustable internal load includes:
- setting a value of an internal resistance by adjusting the value of the adjustable internal load to bring the second regulated frequency nearer to the first regulated frequency.
19. The method of claim 11, further comprising:
- in response to determining to change the number of active stages of the master charge pump, subsequently operating the master charge pump with the second number of active stages.
20. The method of claim 19, further comprising:
- subsequently cyclically repeating the process of determining the level of the adjustable internal load, driving the adjustable internal load, determining whether to change the number of active stages in the master charge pump, and subsequently operating the master charge pump with the determined number of active stages.
21. The method of claim 20, wherein the cyclically repeated determining whether to change the number of active stages in the master charge pump includes determinations both of whether to increase and of whether to decrease the number of active stages in the master charge pump.
22. The method of claim 21, wherein the determinations of whether to alter the number of active stages of the master charge pump includes a repeating sequence of two determinations of whether to increase the number of active stages in the master charge pump and one determination of whether to decrease the number of active stages in the master charge pump.
23. The charge pump system of claim 1, wherein the charge pump system is a peripheral circuit element on a non-volatile memory device.
24. The charge pump system of claim 23, wherein the memory device is an EEPROM based flash memory.
25. The charge pump system of claim 23, wherein the charge pump system is a peripheral circuit element on a monolithic three-dimensional (3D) semiconductor memory device.
26. The charge pump system of claim 25, wherein the semiconductor memory device further comprises a three-dimensional (3D) non-volatile memory that includes multiple memory cells arranged in multiple physical levels above a silicon substrate.
27. The charge pump system of claims 26, wherein the charge pump system is connectable to the three-dimensional (3D) non-volatile memory to supply a programming voltage level thereto from the external output node of the charge pump system.
28. The charge pump system of claims 26, wherein the charge pump system is connectable to the three-dimensional (3D) non-volatile memory to supply an erase voltage level thereto from the external output node of the charge pump system.
29. The method of claim 11, wherein the charge pump system is a peripheral circuit element on a non-volatile memory device to which the charge pump system is connectable to drive as the external load.
30. The method of claim 29, wherein the memory device is an EEPROM based flash memory.
31. The method of claim 29, wherein the charge pump system is a peripheral circuit element on a monolithic three-dimensional semiconductor memory device.
32. The method of claim 31, wherein the semiconductor memory device further comprises a three-dimensional (3D) non-volatile memory that includes multiple memory cells arranged in multiple physical levels above a silicon substrate.
33. The method of claim 32, wherein the charge pump system is connectable to the three-dimensional (3D) non-volatile memory to supply a programming voltage level thereto.
34. The method of claim 32, wherein the charge pump system is connectable to the three-dimensional (3D) non-volatile memory to supply an erase voltage level thereto.
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Type: Grant
Filed: May 30, 2014
Date of Patent: Jan 3, 2017
Assignee: SanDisk Technologies LLC (Plano, TX)
Inventors: Marco Cazzaniga (Palo Alto, CA), Tz-Yi Liu (Palo Alto, CA)
Primary Examiner: My-Trang Ton
Application Number: 14/291,481
International Classification: G05F 1/46 (20060101); H02M 3/18 (20060101);