Patents by Inventor Marco Giandalia

Marco Giandalia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220231606
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Application
    Filed: January 13, 2022
    Publication date: July 21, 2022
    Applicant: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel M. Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 11251709
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: February 15, 2022
    Assignee: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Publication number: 20210281189
    Abstract: A circuit is disclosed. The circuit includes first, second third and fourth diodes connected to form a bridge rectification circuit having a pair of input terminals to receive an AC input signal and a pair of output terminals to deliver a rectified DC signal. The circuit also includes a first semiconductor switch coupled in parallel with the first diode, a second semiconductor switch coupled in parallel with the second diode, and a switch control circuit coupled to the pair of input terminals and arranged to selectively operate the first and second semiconductor switches using power from the AC input signal at the pair of input terminals.
    Type: Application
    Filed: March 3, 2021
    Publication date: September 9, 2021
    Applicant: Navitas Semiconductor Limited
    Inventors: Marco Giandalia, Daniel M. Kinzer, Tao Liu
  • Patent number: 10931200
    Abstract: A current detecting GaN FET is disclosed. The current detecting GaN FET includes a first GaN switch having a first gate, a first drain, a first source, and a first field plate. The current detecting GaN FET also includes a second GaN switch having a second gate, a second drain, a second source, and a second field plate. The current detecting GaN FET also includes a resistor. The first and second gates are electrically connected, the first and second drains are electrically connected, and the resistor is connected between the first and second sources.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: February 23, 2021
    Assignee: Navitas Semiconductor Limited
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Publication number: 20200328682
    Abstract: A current detecting GaN FET is disclosed. The current detecting GaN FET includes a first GaN switch having a first gate, a first drain, a first source, and a first field plate. The current detecting GaN FET also includes a second GaN switch having a second gate, a second drain, a second source, and a second field plate. The current detecting GaN FET also includes a resistor. The first and second gates are electrically connected, the first and second drains are electrically connected, and the resistor is connected between the first and second sources.
    Type: Application
    Filed: May 1, 2020
    Publication date: October 15, 2020
    Applicant: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 10778219
    Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: September 15, 2020
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Publication number: 20200220463
    Abstract: A circuit is disclosed. The circuit includes a current detecting FET, configured to generate a current signal indicative of the value of the current flowing therethrough, an operational transconductance amplifier (OTA) configured to output a current in response to the voltage of the current signal, and a resistor configured to receive the current and to generate a voltage in response to the received current, where the generated voltage is indicative of the value of the current flowing through the current detecting FET. The current detecting FET is configured to become nonconductive in response to the generated voltage indicating that the current flowing through the current detecting FET is greater than a threshold.
    Type: Application
    Filed: March 16, 2020
    Publication date: July 9, 2020
    Applicant: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Patent number: 10666147
    Abstract: A GaN resonant circuit is disclosed. The GaN resonant circuit includes a power switch configured to be selectively conductive according to one or more gate signals, and configured to generate a switch signal indicative of the value of the current flowing therethrough. The GaN resonant circuit also includes a power switch driver, configured to generate the gate signals in response to one or more control signals, where the power switch driver is configured to cause the power switch to become nonconductive in response to the switch signal indicating that the value of the current flowing through the power switch has transitioned across a threshold value.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: May 26, 2020
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Daniel Marvin Kinzer, Tao Liu, Marco Giandalia, Victor Sinow
  • Publication number: 20200044648
    Abstract: A half bridge GaN circuit is disclosed. The half bridge GaN circuit includes a first power node having a first power voltage, where the first power voltage is referenced to a switch voltage at the switch node. The half bridge GaN circuit also includes a VMID power node having a VMID power voltage, where the VMID power voltage is referenced to the first power voltage and is less than the first power voltage by a DC voltage. The half bridge GaN circuit also includes a logic circuit, where a negative power terminal of the logic circuit is connected to the VMID node, and where a positive power terminal of the first logic circuit is connected to the first power node, where the logic circuit is configured to generate a logic output voltage, which controls the conductivity of the high side power switch.
    Type: Application
    Filed: August 28, 2019
    Publication date: February 6, 2020
    Applicant: NAVITAS SEMICONDUCTOR, INC.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Patent number: 10404256
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.
    Type: Grant
    Filed: January 28, 2019
    Date of Patent: September 3, 2019
    Assignee: NAVITAS SEMICONDUCTOR, INC.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Publication number: 20190214993
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.
    Type: Application
    Filed: January 28, 2019
    Publication date: July 11, 2019
    Applicant: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Patent number: 10193554
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side power switch configured to be selectively conductive according to one or more input signals, a high side power switch configured to be selectively conductive according to the one or more input signals, and a high side power switch controller, configured to control the conductivity of the high sigh power switch based on the one or more input signals. The high side power switch controller includes a capacitor, and a logic circuit, wherein the capacitor is configured to capacitively couple a signal based on the input signals to the logic circuit, and the logic circuit is configured to control the conductivity of the high sigh power switch based on the capacitively coupled signal.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: January 29, 2019
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Santosh Sharma, Marco Giandalia, Daniel Marvin Kinzer, Thomas Ribarich
  • Patent number: 9929652
    Abstract: A power circuit is disclosed. The power circuit includes a power capacitor and a power resistor connected to the power capacitor. The power circuit also includes a power integrated circuit, including a GaN-based substrate, a power FET on the substrate, and a driver on the substrate. The driver is configured to charge a gate of the power FET using current from a power node. The power integrated circuit also includes a first power voltage regulator on the substrate, where the driver is configured to receive current from the capacitor through the resistor while the driver charges the gate of the power FET, and where the first power voltage regulator is configured to provide current to the capacitor while the driver does not charge the gate of the power FET.
    Type: Grant
    Filed: December 8, 2016
    Date of Patent: March 27, 2018
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Thomas Ribarich, Santosh Sharma, Ju Zhang, Marco Giandalia, Daniel Marvin Kinzer
  • Patent number: 9831867
    Abstract: A half bridge GaN circuit is disclosed. The circuit includes a low side circuit, which has a low side switch, a low side switch driver configured to drive the low side switch, a first level shift circuit configured to receive a first level shift signal, and a second level shift circuit configured to generate a second level shift signal. The half bridge GaN circuit also includes a high side circuit, which has a high side switch configured to be selectively conductive according to a voltage level of a received high side switch signal, and a high side switch driver configured to generate the high side switch signal in response to the level shift signals. A transition in the voltage of the high side switch signal causes the high side switch driver to prevent additional transitions of the voltage level of the high side switch signal for a period of time.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: November 28, 2017
    Assignee: Navitas Semiconductor, Inc.
    Inventors: Daniel Marvin Kinzer, Santosh Sharma, Ju Zhang, Marco Giandalia, Thomas Ribarich
  • Publication number: 20160372920
    Abstract: An electronic circuit is disclosed and described herein. The circuit includes first and second pins, and an overvoltage protection circuit including a first enhancement-mode transistor. The overvoltage protection circuit is disposed on a GaN-based substrate, and the first enhancement mode transistor is configured to provide overvoltage protection between the first and second pins.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventors: Daniel M. Kinzer, Santosh Sharma, Jason Zhang, Marco Giandalia
  • Patent number: 9473043
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9310819
    Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Alberto Guerra, Sergio Morini, Marco Giandalia
  • Publication number: 20150207432
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9000829
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Publication number: 20140070786
    Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.
    Type: Application
    Filed: August 2, 2013
    Publication date: March 13, 2014
    Applicant: International Rectifier Corporation
    Inventors: Alberto Guerra, Sergio Morini, Marco Giandalia