Patents by Inventor Marco Giandalia

Marco Giandalia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160372920
    Abstract: An electronic circuit is disclosed and described herein. The circuit includes first and second pins, and an overvoltage protection circuit including a first enhancement-mode transistor. The overvoltage protection circuit is disposed on a GaN-based substrate, and the first enhancement mode transistor is configured to provide overvoltage protection between the first and second pins.
    Type: Application
    Filed: June 18, 2015
    Publication date: December 22, 2016
    Inventors: Daniel M. Kinzer, Santosh Sharma, Jason Zhang, Marco Giandalia
  • Patent number: 9473043
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: October 18, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9310819
    Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.
    Type: Grant
    Filed: August 2, 2013
    Date of Patent: April 12, 2016
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Alberto Guerra, Sergio Morini, Marco Giandalia
  • Publication number: 20150207432
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Application
    Filed: March 31, 2015
    Publication date: July 23, 2015
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 9000829
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: April 7, 2015
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Publication number: 20140070786
    Abstract: In one implementation, a power converter includes an output stage integrated circuit (IC) in a group III-V die including a depletion mode group III-V transistor, and a driver IC in a group IV die. The driver IC is configured to drive the output stage IC. In addition, a group IV control switch in the group IV die is cascoded with the depletion mode group III-V transistor. The power converter further includes an overcurrent protection circuit for the depletion mode group III-V transistor, the overcurrent protection circuit monolithically integrated in the group IV die.
    Type: Application
    Filed: August 2, 2013
    Publication date: March 13, 2014
    Applicant: International Rectifier Corporation
    Inventors: Alberto Guerra, Sergio Morini, Marco Giandalia
  • Publication number: 20130271201
    Abstract: According to an exemplary implementation, an integrated circuit (IC) includes a logic circuit monolithically formed on the IC. The logic circuit is configured to generate modulation signals for controlling power switches of a power inverter. The logic circuit generates the modulation signals based on at least one input value. The IC further includes a voltage level shifter monolithically formed on the IC. The voltage level shifter is configured to shift the modulation signals to a voltage level suitable for driving the power switches of the power inverter. The logic circuit can be a digital logic circuit and the input value can be a digital input value. The IC can also include a sense circuit monolithically formed on the IC. The sense circuit is configured to generate the input value.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 17, 2013
    Applicant: International Rectifier Corporation
    Inventors: Marco Giandalia, Toshio Takahashi, Massimo Grasso
  • Patent number: 8013612
    Abstract: An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.
    Type: Grant
    Filed: October 10, 2008
    Date of Patent: September 6, 2011
    Assignee: International Rectifier Corporation
    Inventors: Sergio Morini, Marco Giandalia, David Respigo, Stefano Ruzza, Massimo Grasso
  • Patent number: 7864018
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Grant
    Filed: July 1, 2008
    Date of Patent: January 4, 2011
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Patent number: 7671638
    Abstract: A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.
    Type: Grant
    Filed: June 26, 2008
    Date of Patent: March 2, 2010
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Sergio Morini, Christian Locatelli
  • Patent number: 7592831
    Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit resp
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: September 22, 2009
    Assignee: International Rectifier Corporation
    Inventors: Christian Locatelli, Marco Giandalia
  • Publication number: 20090102488
    Abstract: An integrated ground fault detection circuit in accordance with an embodiment of the present application includes a shunt resistor provided on a positive rail of a DC bus, a high voltage pocket including a sensory circuit connected to the shunt resistor and operable to detect a fault condition indicating a short circuit and a transmitter section operable to continuously transmit a fault condition signal indicating the fault condition and a low voltage pocket including a receiver operable to receive the fault condition signal from the sensory circuit and a logic unit, connected to the receiver, and operable to provide a fault output signal indicating the presence of a fault condition based on the fault condition signal.
    Type: Application
    Filed: October 10, 2008
    Publication date: April 23, 2009
    Applicant: International Rectifier Corporation
    Inventors: Sergio Morini, Marco Giandalia, Davide Respigo, Stefano Ruzza, Massimo Grasso
  • Publication number: 20090002060
    Abstract: A high-side driver in a driver circuit for driving a half-bridge stage having high- and low-side power switching devices series connected at a switched node, the high-side driver driving the high-side power switching device.
    Type: Application
    Filed: June 26, 2008
    Publication date: January 1, 2009
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Marco Giandalia, Sergio Morini, Christian Locatelli
  • Publication number: 20080266043
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Application
    Filed: July 1, 2008
    Publication date: October 30, 2008
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Publication number: 20080258808
    Abstract: A circuit for optimizing charging of a bootstrap capacitor connected to a high side floating supply voltage at a first terminal and to a switched node voltage at a second terminal, the circuit for optimizing being included in a gate driver circuit having high- and low-side driver circuits for driving high- and low-side switches connected at the switched node in a half bridge to provide current to a load, the high-side driver circuit receiving a first control voltage referenced to a first level and the low-side driver circuit receiving a second control voltage referenced to a second level, the bootstrap capacitor providing the high-side floating supply voltage for the high-side driver circuit, the optimizing circuit comprising a bootstrap diode emulator circuit comprising a bootstrap diode emulator driver circuit driving a first switch, the first switch connected between the first terminal of the bootstrap capacitor and a supply voltage for the low side driver circuit; and a phase sense comparator circuit resp
    Type: Application
    Filed: May 20, 2008
    Publication date: October 23, 2008
    Applicant: INTERNATIONAL RECTIFIER CORPORATION
    Inventors: Christian Locatelli, Marco Giandalia
  • Patent number: 7414507
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Grant
    Filed: January 3, 2006
    Date of Patent: August 19, 2008
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Publication number: 20070223154
    Abstract: A circuit in a gate driver circuit controlling a half bridge stage having high and low switches, the gate driver circuit having a high side driving circuit for driving the high switch and low side driving circuit for driving the low switch, the circuit ensuring turning OFF of the high side driving circuit and the high switch. The circuit including an input portion for receiving input signals for the high and low side driving circuits and a shutdown signals; and an output portion for providing SET and RESET signals to the high and low side driving circuits, wherein the high side driving circuit is turned OFF when the input signal for the high side driving circuit is inactive and when the input signal for the low side driving circuit becomes active.
    Type: Application
    Filed: March 19, 2007
    Publication date: September 27, 2007
    Inventors: Christian Locatelli, Marco Giandalia, Marco Palma
  • Publication number: 20060109072
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Application
    Filed: January 3, 2006
    Publication date: May 25, 2006
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Patent number: 7042325
    Abstract: A planar transformer arrangement and method provide isolation between an input signal and an output signal.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: May 9, 2006
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Massimo Grasso, Marco Passoni
  • Patent number: 6987678
    Abstract: A power supply has an output circuit for a secondary stage of a converter that switches on and off a switching device such that the output voltage of the converter is regulated across a capacitor without use of an inductor in the output circuit. For example, the switching device is a semiconductor field effect transistor controlled by a comparator. The output circuit may be used with a switch mode power supply comprising a coreless, planar isolation transformer.
    Type: Grant
    Filed: October 23, 2003
    Date of Patent: January 17, 2006
    Assignee: International Rectifier Corporation
    Inventors: Marco Giandalia, Marco Passoni