Patents by Inventor Marco Zuniga

Marco Zuniga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371902
    Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate includes (a) a first gate conductor and a second gate conductor each extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure in a thickness direction, (b) a first separation dielectric layer separating the first gate conductor from the second gate conductor within the vertical gate, and (c) a gate dielectric layer separating each of the first gate conductor and the second gate conductor from the silicon semiconductor structure.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 5, 2019
    Inventors: Tom K. Castro, Marco A. Zuniga, Badredin Fatemizadeh, Adam Brand, John Xia, Rajwinder Singh, Min Xu, Chi-Nung Ni
  • Publication number: 20190259830
    Abstract: A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Inventors: Vijay Parthasarathy, Vipindas Pala, Marco A. Zuniga
  • Publication number: 20190260376
    Abstract: A current sense device includes a reference transistor for electrically coupling to a power transistor, a sense transistor for electrically coupling to the power transistor, and control circuitry. The control circuitry is configured to (a) control current through the sense transistor such that a voltage at the sense transistor has a predetermined relationship to a voltage at the power transistor, and (b) control current through the sense transistor according to one or more operating conditions at the reference transistor, to compensate for aging of the power transistor.
    Type: Application
    Filed: February 20, 2019
    Publication date: August 22, 2019
    Inventors: Marco A. Zuniga, Michael David McJimsey, Brett A. Miwa, Chi-Teh Chiang, Ilija Jergovic, Urs Harald Mader
  • Publication number: 20190259751
    Abstract: A multi-transistor device includes first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region. In certain embodiments, the first LDMOS transistor includes a first drift region, the second LDMOS transistor includes a second drift region, and the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 22, 2019
    Inventors: Vipindas Pala, Vijay Parthasarathy, Badredin Fatemizadeh, Marco A. Zuniga, John Xia
  • Publication number: 20190181237
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.
    Type: Application
    Filed: February 4, 2019
    Publication date: June 13, 2019
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
  • Patent number: 10284072
    Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: May 7, 2019
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 10269916
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: April 23, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
  • Patent number: 10243467
    Abstract: The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: March 26, 2019
    Assignee: Volterra Semiconductor LLC
    Inventors: Chiteh Chiang, Marco A. Zuniga, Yang Lu
  • Patent number: 10199475
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.
    Type: Grant
    Filed: May 23, 2017
    Date of Patent: February 5, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
  • Publication number: 20180350980
    Abstract: A lateral double-diffused metal-oxide-semiconductor transistor includes a silicon semiconductor structure and a vertical gate. The vertical gate include a (a) gate conductor extending from a first outer surface of the silicon semiconductor structure into the silicon semiconductor structure and (b) a gate dielectric layer including a least three dielectric sections. Each of the at least three dielectric sections separates the gate conductor from the silicon semiconductor structure by a respective separation distance, where each of the respective separation distances is different from each other of the respective separation distances.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 6, 2018
    Inventors: Tom K. Castro, Rajwinder Singh, Badredin Fatemizadeh, Adam Brand, John Xia, Chi-Nung Ni, Marco A. Zuniga
  • Patent number: 10147801
    Abstract: The present application features a transistor that includes an n-well region implanted into a surface of a substrate, a gate region, and a source region, and a drain region. The source region is on a first side of the gate region and includes a p-body region in the n-well region. An n+ region and a p+ region are implanted in the p-body region such that the p+ region is below the n+ region. The drain region is on a second side of the gate region and includes an n+ region.
    Type: Grant
    Filed: August 10, 2012
    Date of Patent: December 4, 2018
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Yang Lu, Badredin Fatemizadeh, Jayasimha Prasad, Amit Paul, Jun Ruan
  • Publication number: 20180109192
    Abstract: The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.
    Type: Application
    Filed: December 18, 2017
    Publication date: April 19, 2018
    Inventors: Chiteh Chiang, Marco A. Zuniga, Yang Lu
  • Patent number: 9847722
    Abstract: The subject matter of this document can be embodied in a method that includes a voltage regulator having an input terminal and an output terminal. The voltage regulator includes a high-side transistor between the input terminal and an intermediate terminal, and a low-side transistor between the intermediate terminal and ground. The voltage regulator includes a low-side driver circuit including a capacitor and an inverter. The output of the inverter is connected to the gate of the low-side transistor. The voltage regulator also includes a controller that drives the high-side and low-side transistors to alternately couple the intermediate terminal to the input terminal and ground. The controller is configured to drive the low-side transistor by controlling the inverter. The voltage regulator further includes a switch coupled to the low-side driver circuit. The switch is configured to block charge leakage out of the capacitor during an off state of the low-side transistor.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: December 19, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Chiteh Chiang, Marco A. Zuniga, Yang Lu
  • Publication number: 20170346477
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure, a dielectric layer at least partially disposed in a trench of the silicon semiconductor structure in a thickness direction, and a gate conductor embedded in the dielectric layer and extending into the trench in the thickness direction. The dielectric layer and the gate conductor are at least substantially symmetric with respect to a center axis of the trench extending in the thickness direction, as seen when the LDMOS transistor is viewed cross-sectionally in a direction orthogonal to the lateral and thickness directions.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 30, 2017
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
  • Publication number: 20170346476
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect transistor includes a silicon semiconductor structure, first and second gate structures, and a trench dielectric layer. The first and second gate structures are disposed on the silicon semiconductor structure and separated from each other in a lateral direction. The trench dielectric layer is disposed in a trench in the silicon semiconductor structure and extends at least partially under each of the first and second gate structures in a thickness direction orthogonal to the lateral direction.
    Type: Application
    Filed: May 23, 2017
    Publication date: November 30, 2017
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh, Vijay Parthasarathy
  • Publication number: 20170338731
    Abstract: A voltage regulator includes a high-side device, a low-side device, and a controller. The high-side device includes first and second transistors each coupled between an input terminal and an intermediate terminal, where the first transistor has a higher breakdown voltage than the second transistor. The low-side device is coupled between the intermediate terminal and a ground terminal. The controller is configured to drive the high-side and low-side devices to (a) alternately couple the intermediate terminal to the input terminal and the ground terminal and (b) cause the first transistor to control a voltage across the second transistor during switching transitions of the second transistor.
    Type: Application
    Filed: July 28, 2017
    Publication date: November 23, 2017
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 9806523
    Abstract: A switching circuit for extracting power from an electric power source includes (1) an input port for electrically coupling to the electric power source, (2) an output port for electrically coupling to a load, (3) a first switching device configured to switch between its conductive state and its non-conductive state to transfer power from the input port to the output port, (4) an intermediate switching node that transitions between at least two different voltage levels at least in part due to the first switching device switching between its conductive state and its non-conductive state, and (5) a controller for controlling the first switching device to maximize an average value of a voltage at the intermediate switching node.
    Type: Grant
    Filed: May 18, 2015
    Date of Patent: October 31, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Anthony J. Stratakos, Michael D. McJimsey, Ilija Jergovic, Alexandr Ikriannikov, Artin Der Minassians, Kaiwei Yao, David B. Lidsky, Marco A. Zuniga, Ana Borisavljevic
  • Publication number: 20170263766
    Abstract: A lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistor includes a silicon semiconductor structure including (a) a base layer, (b) a p-type reduced surface field effect (RESURF) layer disposed over the base layer in a thickness direction, (c) a p-body disposed over the p-type RESURF layer in the thickness direction, (d) a source p+ region and a source n+ region each disposed in the p-body, (e) a high-voltage n-type laterally-diffused drain (HVNLDD) disposed adjacent to the p-body in a lateral direction orthogonal to the thickness direction, the HVNLDD contacting the p-type RESURF layer, and (f) a drain n+ region disposed in the HVNLDD. The LDMOS transistor further includes (a) a first dielectric layer disposed on the silicon semiconductor structure in the thickness direction over at least part of the p-body and the HVNLDD and (b) a first gate conductor disposed on the first dielectric layer in the thickness direction.
    Type: Application
    Filed: March 13, 2017
    Publication date: September 14, 2017
    Inventors: John Xia, Marco A. Zuniga, Badredin Fatemizadeh
  • Patent number: 9722483
    Abstract: A voltage regulator has an input terminal and a ground terminal. The voltage regulator includes a high-side device, a low side device, and a controller. The high-side device is coupled between the input terminal and an intermediate terminal. The high-side device includes first and second transistors each coupled between the input terminal and the intermediate terminal, such that the first transistor controls a drain-source switching voltage of the second transistor. The low-side device is coupled between the intermediate terminal and the ground terminal. The controller drives the high-side and low-side devices to alternately couple the intermediate terminal to the input terminal and the ground terminal.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 1, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Marco A. Zuniga, Chiteh Chiang, Yang Lu, Badredin Fatemizadeh, Amit Paul, Jun Ruan, Craig Cassella
  • Patent number: 9698599
    Abstract: An electric power system includes N electric power sources and N switching circuits, where N is an integer greater than one. Each switching circuit includes an input port electrically coupled to a respective one of the N electric power sources, an output port, and a first switching device adapted to switch between its conductive and non-conductive states to transfer power from the input port to the output port. The output ports of the N switching circuits are electrically coupled in series and to a load to establish an output circuit. Each of the N switching circuits uses an interconnection inductance of the output circuit as a primary energy storage inductance of the switching circuit.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: July 4, 2017
    Assignee: Volterra Semiconductor LLC
    Inventors: Anthony J. Stratakos, Michael D. McJimsey, Ilija Jergovic, Alexandr Ikriannikov, Artin Der Minassians, Kaiwei Yao, David B. Lidsky, Marco A. Zuniga, Ana Borisavljevic