Patents by Inventor Marco Zuniga

Marco Zuniga has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7999318
    Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.
    Type: Grant
    Filed: December 24, 2008
    Date of Patent: August 16, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You
  • Patent number: 7984507
    Abstract: This disclosure provides a document access method and system. The document access method and system are based on a social network model which interconnects members of the social network as a function of trust. This framework provides a basis for documents to be accessed by members which are not directly specified by a document's owner, while providing a certain degree of document security.
    Type: Grant
    Filed: December 7, 2007
    Date of Patent: July 19, 2011
    Assignee: Xerox Corporation
    Inventors: Marco A. Zuniga, Steven J. Harrington
  • Patent number: 7981739
    Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.
    Type: Grant
    Filed: February 22, 2010
    Date of Patent: July 19, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Publication number: 20110133274
    Abstract: A LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Application
    Filed: February 14, 2011
    Publication date: June 9, 2011
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7888222
    Abstract: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Grant
    Filed: February 22, 2007
    Date of Patent: February 15, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7868378
    Abstract: An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.
    Type: Grant
    Filed: July 17, 2006
    Date of Patent: January 11, 2011
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You, Yang Lu
  • Publication number: 20100173458
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
    Type: Application
    Filed: March 1, 2010
    Publication date: July 8, 2010
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7671411
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: March 2, 2010
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7666731
    Abstract: A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: February 23, 2010
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7615822
    Abstract: A transistor has a source that includes a first impurity region with a first volume and a first surface area on a surface of the transistor. The transistor also has a drain that includes a second impurity region with a second volume and a second surface area on a surface of the transistor, a third impurity region with a third volume that overlaps and extends deeper than the second volume of the second impurity region, and a fourth impurity region with a fourth volume and a third surface area. The third surface area is located in the second surface area of the second impurity region. Additionally, the second and third impurity regions have a lower concentration of impurities than the fourth impurity region. The transistor also has a gate to control a depletion region between the source and the drain.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: November 10, 2009
    Assignee: Volterra Semiconductor Corporation
    Inventor: Marco A. Zuniga
  • Publication number: 20090224333
    Abstract: A transistor includes a substrate, a well formed in the substrate, a drain including a first impurity region implanted in the well, a source including a second impurity region implanted in the well and spaced apart from the first impurity region, a channel for current flow from the drain to the source, and a gate to control a depletion region between the source and the drain The channel has an intrinsic breakdown voltage, and the well, drain and source are configured to provide an extrinsic breakdown voltage lower than the intrinsic breakdown voltage and such that breakdown occurs in a breakdown region in the well located outside the channel and adjacent the drain or the source.
    Type: Application
    Filed: January 14, 2009
    Publication date: September 10, 2009
    Inventors: Yang Lu, Budong You, Marco A. Zuniga, Hamza Yilmaz
  • Publication number: 20090224739
    Abstract: A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.
    Type: Application
    Filed: December 24, 2008
    Publication date: September 10, 2009
    Inventors: Marco A. Zuniga, Budong You
  • Publication number: 20090151002
    Abstract: This disclosure provides a document access method and system. The document access method and system are based on a social network model which interconnects members of the social network as a function of trust. This framework provides a basis for documents to be accessed by members which are not directly specified by a document's owner, while providing a certain degree of document security.
    Type: Application
    Filed: December 7, 2007
    Publication date: June 11, 2009
    Applicant: Xerox Corporation
    Inventors: Marco A. Zuniga, Steven J. Harrington
  • Patent number: 7465621
    Abstract: A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the transistor to have a second surface area in the first surface area of the first impurity region. A gate oxide is formed after implantation of the second impurity region between a source region and the drain region of the transistor, and the gate oxide is covered with a conductive material. A third impurity region of the opposite second type and a fourth impurity region of the first type are implanted into the source region of the transistor in the first surface area. A fifth impurity region of the opposite second type is implanted into the drain region of the transistor in the second surface area of the second impurity region.
    Type: Grant
    Filed: September 21, 2005
    Date of Patent: December 16, 2008
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga, Andrew J. Burstein
  • Patent number: 7405443
    Abstract: Method and apparatus for providing a lateral double-diffused MOSFET (LDMOS) transistor having a dual gate. The dual gate includes a first gate and a second gate. The first gate includes a first oxide layer formed over a substrate, and the second gate includes a second oxide layer formed over the substrate. The first gate is located a pre-determined distance from the second gate. A digitally implemented voltage regulator is also provided that includes a switching circuit having a dual gate LDMOS transistor.
    Type: Grant
    Filed: January 7, 2005
    Date of Patent: July 29, 2008
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You
  • Patent number: 7405117
    Abstract: A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed.
    Type: Grant
    Filed: May 15, 2006
    Date of Patent: July 29, 2008
    Assignee: Volterra Semiconductor Corporation
    Inventors: Marco A. Zuniga, Budong You
  • Publication number: 20070207600
    Abstract: Methods and systems for monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow are described.
    Type: Application
    Filed: March 2, 2007
    Publication date: September 6, 2007
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Budong You, Marco A. Zuniga
  • Publication number: 20070166896
    Abstract: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Application
    Filed: February 22, 2007
    Publication date: July 19, 2007
    Applicant: VOLTERRA SEMICONDUCTOR CORPORATION
    Inventors: Budong You, Marco Zuniga
  • Patent number: 7230470
    Abstract: A power switch, and a method, for use with a power switch having a field-effect transistor (FET) including source, drain and gate terminals. The power switch includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; and, a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate. The second FET has a gate length (LG) that is greater than or less than an LG of the first FET and has a length of a drain (LD) that is greater than or less than an LD of the first FET. The power switch further includes a control circuit coupled to the gate terminal, the first gate, and the second gate.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 12, 2007
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga
  • Patent number: 7220633
    Abstract: A method of monolithically fabricating an LDMOS transistor with a fabrication process that is compatible with a sub-micron CMOS fabrication process. The specification further describes an LDMOS transistor. The LDMOS transistor is implemented in a first impurity region on a substrate. The LDMOS transistor has a source that includes a second impurity region. The second impurity region is implanted into the surface of the substrate within the first impurity region. Additionally, the LDMOS transistor has a drain that includes a third impurity region. The third impurity region is implanted into the surface of the substrate within the first impurity region. The third impurity region is spaced a predetermined distance away from a gate of the LDMOS transistor. The drain of the LDMOS transistor further includes a fourth impurity region within the third impurity region. The fourth impurity region provides an ohmic contact for the drain.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: May 22, 2007
    Assignee: Volterra Semiconductor Corporation
    Inventors: Budong You, Marco A. Zuniga