Abstract: A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

Abstract: A device and methods of forming the same are described. The device includes a substrate, source/drain regions disposed over the substrate, a ferroelectric layer disposed over the substrate, a gate electrode in contact with the ferroelectric layer, a first conductive contact disposed at a first end of the gate electrode, and a second conductive contact disposed at a second end opposite the first end of the gate electrode. The first and second conductive contacts are configured to allow a current to flow from the first conductive contact through the gate electrode to the second conductive contact.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Abstract: A semiconductor device includes an oxide semiconductor stack, a first gate, a first contact structure, and a second contact structure. The oxide semiconductor stack includes an n-type oxide semiconductor layer and a p-type oxide semiconductor layer stacked on each other. The first gate is over the oxide semiconductor stack. The first contact structure and the second contact structure are at opposite sides of the first gate and electrically connected to the oxide semiconductor stack.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Abstract: A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Abstract: A semiconductor device includes a substrate, a main circuit disposed over a front surface of the substrate, and a backside power delivery circuit disposed over a back surface of the substrate. The backside power delivery circuit includes a first main power supply wiring for supplying a first voltage, a second main power supply wiring for supplying a second voltage, a first local power supply wiring, and a first switch coupled to the first main power supply wiring and the first local power supply wiring. The first main power supply wiring, the second main power supply wiring and the first local power supply wiring are embedded in a first back side insulating layer disposed over the back surface of the substrate. The first local power supply wiring is coupled to the main circuit via a first through-silicon via (TSV) passing through the substrate for supplying the first voltage.

Abstract: The present disclosure relates to an integrated chip including a channel structure on a first substrate. A gate electrode overlies the channel structure. A first source/drain structure abuts the channel structure and is offset from the gate electrode. A conductive structure is disposed on the first substrate and underlies the first source/drain structure. A first contact extends from the first source/drain structure to the conductive structure.

Abstract: A semiconductor structure includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Abstract: A semiconductor device includes a substrate, a semiconductor fin, a source/drain structure, a first buried power line, a contact, a first through substrate via (TSV), and a second TSV. The substrate has a well region extending a front-side surface of the substrate into the substrate. The semiconductor fin is on the well region. The source/drain structure is on the semiconductor fin. The first buried power line is electrically coupled to the source/drain structure on the first semiconductor fin. The first buried power line has a length extending along a lengthwise direction of the first semiconductor fin and a height extending within the well region. The first TSV extends from a back-side surface of the substrate through the substrate to the first buried power line. The second TSV extends from the back-side surface of the substrate to the well region.

Abstract: Some embodiments relate to an integrated chip including a memory device. The memory device includes a bottom electrode disposed over a semiconductor substrate. An upper electrode is disposed over the bottom electrode. An intercalated metal/dielectric structure is sandwiched between the bottom electrode and the upper electrode. The intercalated metal/dielectric structure comprises a lower dielectric layer over the bottom electrode, an upper dielectric layer over the lower dielectric layer, and a first metal layer separating the upper dielectric layer from the lower dielectric layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a first gate electrode, a ferroelectric insulating layer over the first gate electrode, a semiconductor member over the ferroelectric insulating layer, a gate dielectric layer over the semiconductor member, and a second gate electrode over the gate dielectric layer.

Abstract: A semiconductor device includes a channel layer, source/drain contacts, and first barrier liners. The channel layer includes an oxide semiconductor material. The source/drain contacts are disposed in electrical contact with the channel layer. The first barrier liners surround the source/drain contacts, respectively, and include a hydrogen barrier material so as to prevent hydrogen from diffusion through the first barrier liners to the channel layer.

Abstract: Semiconductor devices and methods of forming the same are provided. A semiconductor device according to the present disclosure includes a ferroelectric structure including a channel region and a source/drain region, a gate dielectric layer disposed over the channel region of the ferroelectric structure, a gate electrode disposed on the gate dielectric layer, and a source/drain contact disposed on the source/drain region of the ferroelectric structure. The ferroelectric structure includes gallium nitride, indium nitride, or indium gallium nitride. The ferroelectric structure is doped with a dopant.

Abstract: In a method of forming a gate-all-around field effect transistor (GAA FET), a fin structure is formed. The fin structure includes a plurality of stacked structures each comprising a dielectric layer, a CNT over the dielectric layer, a support layer over the CNT. A sacrificial gate structure is formed over the fin structure, an isolation insulating layer is formed, a source/drain opening is formed by patterning the isolation insulating layer, the support layer is removed from each of the plurality of stacked structures in the source/drain opening, and a source/drain contact layer is formed in the source/drain opening. The source/drain contact is formed such that the source/drain contact is in direct contact with only a part of the CNT and a part of the dielectric layer is disposed between the source/drain contact and the CNT.

Abstract: The current disclosure describes techniques for forming semiconductor structures having multiple semiconductor strips configured as channel portions. In the semiconductor structures, diffusion break structures are formed after the gate structures are formed so that the structural integrity of the semiconductor strips adjacent to the diffusion break structures will not be compromised by a subsequent gate formation process. The diffusion break extends downward from an upper surface until all the semiconductor strips of the adjacent channel portions are truncated by the diffusion break.

Abstract: In a method of manufacturing a semiconductor device, a dummy gate structure is formed over a channel region of a semiconductor layer, a source/drain epitaxial layer is formed on opposing sides of the dummy gate structure, a planarization operation is performed on the source/drain epitaxial layer, the planarized source/drain epitaxial layer is patterned, the dummy gate structure is removed to form a gate space, and a metal gate structure is formed in the gate space.

Abstract: The present disclosure relates to an integrated chip including a ferroelectric layer. The ferroelectric layer includes a ferroelectric material. A first relaxation layer including a first material, different from the ferroelectric material, is on a first side of the ferroelectric layer. A second relaxation layer including a second material, different from the ferroelectric material, is on a second side of the ferroelectric layer, opposite the first side. A Young’s modulus of the first relaxation layer is less than a Young’s modulus of the ferroelectric layer.

Abstract: A semiconductor device includes a storage element layer and a selector. The selector is electrically coupled to the storage element layer, and includes a first insulating layer, a second insulating layer, a third insulating layer, a first conductive layer and a second conductive layer. The first insulating layer, the second insulating layer and the third insulating layer are stacked up in sequence, wherein the second insulating layer is sandwiched in between the first insulating layer and the third insulating layer, and the first insulating layer and the third insulating layer include materials with higher band gap as compared with a material of the second insulating layer. The first conductive layer is connected to the first insulting layer, and the second conductive layer is connected to the third insulating layer.

Abstract: In a method of forming a gate-all-around field effect transistor, a gate structure is formed surrounding a channel portion of a carbon nanotube. An inner spacer is formed surrounding a source/drain extension portion of the carbon nanotube, which extends outward from the channel portion of the carbon nanotube. The inner spacer includes two dielectric layers that form interface dipole. The interface dipole introduces doping to the source/drain extension portion of the carbon nanotube.