Patents by Inventor Marek Hytha

Marek Hytha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978771
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Grant
    Filed: December 21, 2022
    Date of Patent: May 7, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Patent number: 11923418
    Abstract: A semiconductor device may include a first single crystal silicon layer having a first percentage of silicon 28; a second single crystal silicon layer having a second percentage of silicon 28 higher than the first percentage of silicon 28; and a superlattice between the first and second single crystal silicon layers. The superlattice may include stacked groups of layers, with each group of layers including stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: March 5, 2024
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
  • Publication number: 20240063268
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Application
    Filed: November 3, 2023
    Publication date: February 22, 2024
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Publication number: 20230411557
    Abstract: A semiconductor device may include at least one semiconductor layer including a superlattice therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The semiconductor device may further include quantum dots spaced apart in the at least one semiconductor layer above the superlattice and including a different semiconductor material than the semiconductor layer.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 21, 2023
    Inventors: MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
  • Publication number: 20230411491
    Abstract: A method for making a semiconductor device may include forming at least one semiconductor layer including a superlattice therein. The superlattice may include a plurality of stacked groups of layers, with each group of layers including stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include forming quantum dots spaced apart in the at least one semiconductor layer above the superlattice and including a different semiconductor material than the semiconductor layer.
    Type: Application
    Filed: June 21, 2023
    Publication date: December 21, 2023
    Inventors: MAREK HYTHA, NYLES WYNN CODY, ROBERT J. MEARS, HIDEKI TAKEUCHI, KEITH DORAN WEEKS
  • Patent number: 11848356
    Abstract: A method for making a semiconductor device may include forming a superlattice adjacent a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 19, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Publication number: 20230395374
    Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.
    Type: Application
    Filed: August 23, 2023
    Publication date: December 7, 2023
    Inventors: MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY, HIDEKI TAKEUCHI
  • Patent number: 11837634
    Abstract: A semiconductor device may include a semiconductor layer and a superlattice adjacent the semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one non-semiconductor monolayer in a first group of layers of the superlattice may comprise oxygen and be devoid of carbon, and the at least one non-semiconductor monolayer in a second group of layers of the superlattice may comprise carbon.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: December 5, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Keith Doran Weeks, Nyles Wynn Cody, Marek Hytha, Robert J. Mears, Robert John Stephenson, Hideki Takeuchi
  • Publication number: 20230361178
    Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.
    Type: Application
    Filed: June 23, 2023
    Publication date: November 9, 2023
    Inventors: MAREK HYTHA, NYLES WYNN CODY, KEITH DORAN WEEKS
  • Patent number: 11810784
    Abstract: A method for making a semiconductor device may include forming a first single crystal silicon layer having a first percentage of silicon 28, and forming a superlattice above the first single crystal silicon layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers comprising a plurality of stacked base silicon monolayers defining a base silicon portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base silicon portions. The method may further include forming a second single crystal silicon layer above the superlattice having a second percentage of silicon 28 higher than the first percentage of silicon 28.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: November 7, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody, Hideki Takeuchi
  • Patent number: 11728385
    Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: August 15, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
  • Patent number: 11721546
    Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: August 8, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
  • Patent number: 11682712
    Abstract: A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18O greater than 10 percent.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: June 20, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
  • Publication number: 20230136797
    Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer, the superlattice including a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate adjacent the semiconductor layer, epitaxially growing an active semiconductor device layer above the semiconductor layer and accumulated non-semiconductor atoms after the selective etching, and forming at least one circuit in the epitaxially grown active semiconductor device layer.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Inventors: MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
  • Publication number: 20230135451
    Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.
    Type: Application
    Filed: October 28, 2021
    Publication date: May 4, 2023
    Inventors: MAREK HYTHA, KEITH DORAN WEEKS, NYLES WYNN CODY
  • Publication number: 20230122723
    Abstract: A method for making a semiconductor gate-all-around (GAA) device may include forming source and drain regions on a semiconductor substrate, forming a plurality of semiconductor nanostructures extending between the source and drain regions, and forming a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, the method may include forming at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Publication number: 20230121774
    Abstract: A semiconductor gate-all-around (GAA) device may include a semiconductor substrate, source and drain regions on the semiconductor substrate, a plurality of semiconductor nanostructures extending between the source and drain regions, and a gate surrounding the plurality of semiconductor nanostructures in a gate-all-around arrangement. Furthermore, at least one superlattice may be within at least one of the nanostructures. The at least one superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions.
    Type: Application
    Filed: December 21, 2022
    Publication date: April 20, 2023
    Inventors: KEITH DORAN WEEKS, NYLES WYNN CODY, MAREK HYTHA, ROBERT J. MEARS, ROBERT JOHN STEPHENSON, HIDEKI TAKEUCHI
  • Patent number: 11631584
    Abstract: A method for making a semiconductor device may include forming a superlattice above a semiconductor layer. The superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The method may further include selectively etching the superlattice to remove semiconductor atoms and cause non-semiconductor atoms to accumulate and define an etch stop layer.
    Type: Grant
    Filed: October 28, 2021
    Date of Patent: April 18, 2023
    Assignee: ATOMERA INCORPORATED
    Inventors: Marek Hytha, Keith Doran Weeks, Nyles Wynn Cody
  • Publication number: 20220384579
    Abstract: A semiconductor device may include a semiconductor layer, and a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may include an atomic percentage of 18O greater than 10 percent.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Marek Hytha, Nyles Wynn Cody, Keith Doran Weeks
  • Publication number: 20220384612
    Abstract: A method for making a semiconductor device may include forming a semiconductor layer, and forming a superlattice adjacent the semiconductor layer and including stacked groups of layers. Each group of layers may include stacked base semiconductor monolayers defining a base semiconductor portion, and at least one oxygen monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one oxygen monolayer of a given group of layers may comprise an atomic percentage of 18O greater than 10 percent.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: MAREK HYTHA, Nyles Wynn Cody, Keith Doran Weeks