Patents by Inventor Maria Cristina B. Estacio
Maria Cristina B. Estacio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9583454Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: GrantFiled: December 13, 2011Date of Patent: February 28, 2017Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Patent number: 9159656Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: September 5, 2013Date of Patent: October 13, 2015Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 9147627Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.Type: GrantFiled: November 12, 2009Date of Patent: September 29, 2015Assignee: Fairchild Semiconductor CorporationInventors: Seung-Yong Choi, Ti Ching Shian, Maria Cristina B. Estacio
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Publication number: 20140167238Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: September 5, 2013Publication date: June 19, 2014Applicant: FAIRCHILD SEMICONDUCTOR CORPORATIONInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8664752Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: March 26, 2012Date of Patent: March 4, 2014Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8513059Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: GrantFiled: July 19, 2011Date of Patent: August 20, 2013Assignee: Fairchild Semiconductor CorporationInventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Publication number: 20120181675Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: March 26, 2012Publication date: July 19, 2012Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Patent number: 8183088Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: GrantFiled: June 25, 2010Date of Patent: May 22, 2012Assignee: Fairchild Semiconductor CorporationInventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Byoung-Ok Lee
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Publication number: 20120083071Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: ApplicationFiled: December 13, 2011Publication date: April 5, 2012Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Patent number: 8106501Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: GrantFiled: December 12, 2008Date of Patent: January 31, 2012Assignee: Fairchild Semiconductor CorporationInventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Publication number: 20110272794Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: ApplicationFiled: July 19, 2011Publication date: November 10, 2011Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Patent number: 8008759Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: GrantFiled: June 24, 2010Date of Patent: August 30, 2011Assignee: Fairchild Semiconductor CorporationInventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Patent number: 7972906Abstract: A clip structure and semiconductor die package. The clip structure includes a first portion and a second portion, with a connecting structure located between the first and second portion. The clip structure is substantially planar. The semiconductor die package includes a semiconductor die located between a leadframe structure and a clip structure. Slots are formed within the molding material covering portions of the semiconductor die package. The slots are located between a first portion and the second portion of the clip structure, and the slot overlap with the semiconductor die.Type: GrantFiled: March 7, 2008Date of Patent: July 5, 2011Assignee: Fairchild Semiconductor CorporationInventors: Erwin Victor R. Cruz, Maria Cristina B. Estacio
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Patent number: 7838340Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: GrantFiled: June 24, 2010Date of Patent: November 23, 2010Assignee: Fairchild Semiconductor CorporationInventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Publication number: 20100258925Abstract: Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die.Type: ApplicationFiled: June 25, 2010Publication date: October 14, 2010Inventors: Oseob Jeon, Yoonhwa Choi, Boon Huan Gooi, Maria Cristina B. Estacio, David Chong, Tan Teik Keng, Shibaek Nam, Rajeev Joshi, Chung-Lin Wu, Venkat Iyer, Lay Yeap Lim, Byoung-Ok Lee
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Publication number: 20100258923Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Publication number: 20100258924Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: ApplicationFiled: June 24, 2010Publication date: October 14, 2010Inventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Patent number: 7768105Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.Type: GrantFiled: January 24, 2007Date of Patent: August 3, 2010Assignee: Fairchild Semiconductor CorporationInventors: Erwin Victor Cruz, Maria Cristina B. Estacio
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Publication number: 20100148346Abstract: A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an outer surface of the clip structure. The clip structure is electrically coupled to the semiconductor die. The semiconductor die package further comprises a leadframe structure comprising a die attach pad and a plurality of leads extending from the die attach pad. The semiconductor die is on the die attach pad of the leadframe structure. A second molding material covers at least a portion of the semiconductor die and the leadframe structure. The semiconductor die package also includes a heat slug and a thermally conductive material coupling the heat slug to the exposed surface of the clip structure.Type: ApplicationFiled: December 12, 2008Publication date: June 17, 2010Inventors: Maria Clemens Y. Quinones, Maria Cristina B. Estacio
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Publication number: 20100127375Abstract: Wafer-level chip scale (WLCSP) semiconductor packages and methods for making and using the same are described. The WLCSP semiconductor packages contain a grid array of land pads rather than solder balls or solder bumps. The land pads can be provided directly on a semiconductor wafer by using a leadframe interconnect structure that has been formed from a leadframe. The land pads can be used to mount the WLCSP to a circuit board. Such a configuration allows the formation of a thinner chip scale semiconductor package using a simpler manufacturing process, thereby reducing costs and improving performance. Other embodiments are described.Type: ApplicationFiled: November 21, 2008Publication date: May 27, 2010Inventors: Manolito Galera, Leocadio Morona Alabin, Maria Cristina B. Estacio