Abstract: A flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package.

Abstract: The invention provides a flip chip molded leadless package (MLP) with electrical paths printed in conducting ink. The MLP includes a taped leadframe with a plurality of leads and a non-conducting tape placed thereon. The electrical paths are printed on the tape to connect the features of the semiconductor device to the leads and an encapsulation layer protects the package. In a second embodiment, the MLP includes a pre-molded leadframe with the electrical paths printed directly thereon. The present invention also provides a method of fabricating the semiconductor package according to each embodiment.

Abstract: A method for making a premolded clip structure is disclosed. The method includes obtaining a first clip and a second clip, and forming a molding material around the first clip comprising a first surface and the second clip comprising a second surface. The first surface of the first clip structure and the second surface of the second clip structure are exposed through the molding material, and a premolded clip structure is then formed.

Abstract: Provided are a molded leadless package, and a sawing type molded leadless package and method of manufacturing same. The molded leadless package includes a lead frame pad having first and second surfaces opposite to each other. A semiconductor chip is adhered to the first surface of the lead frame pad. A lead is electrically coupled to the semiconductor chip. A molding material covers the lead frame pad, the semiconductor chip, and the lead and exposes a portion of the lead and a portion of the second surface of the lead frame pad. A step difference is formed between a surface of the molding material covering the second surface of the lead frame pad and the second surface of the lead frame pad itself. The sawing type molded leadless package includes a short-circuit preventing member that is post-shaped or convex, and protruding from the lower surface of the die pad.

Abstract: A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.

Abstract: A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such that the copper clip contacts drain regions of the bumped die and a lead rail. The chip device is manufactured by flip chipping a bumped die onto the leadframe and placing the copper clip on a backside of the trench die such that the backside of the trench die is coupled to the lead rail. The process involves reflowing the solder bumps on the bumped die and solder paste that is placed between the copper clip and the backside of the bumped die.

Abstract: A chip device including a leadframe that includes source and gate connections, a bumped die including solder bumps on a top side that is attached to the leadframe such that the solder bumps contact the source and gate connections, and a copper clip attached to the backside of the bumped die such that the copper clip contacts drain regions of the bumped die and a lead rail. The chip device is manufactured by flip chipping a bumped die onto the leadframe and placing the copper clip on a backside of; the trench die such that the backside of the trench die is coupled to the lead rail. The process involves reflowing the solder bumps on the bumped die and solder paste that is placed between the copper clip and the backside of the bumped die.

Abstract: A method for forming a semiconductor die package is provided. The method comprises: forming a semiconductor die including a source contact region and a gate contact region at a first side and a drain contact region at a second side; forming a first conductive path on the semiconductor die extending from the source contact region at the first side to the second side; forming a second conductive path on the semiconductor die extending from the gate contact region at the first side to the second side; and attaching the semiconductor die to a circuit substrate so that the second side is proximate to the circuit substrate and the first side is distal to circuit substrate.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package includes a circuit substrate including a conductive region. A semiconductor die is on the circuit substrate. The semiconductor die includes an edge and a recess at the edge. A solder joint couples the semiconductor die and the conductive region through the recess.

Abstract: A multichip module is disclosed. In one embodiment, the multichip module includes a substrate having a first side and a second side, the first side being opposite to the first side. A driver chip is at the first side of the substrate. A semiconductor die comprising a vertical transistor is at the second side of the substrate. The driver chip and the semiconductor die are in electrical communication through the substrate.

Abstract: A semiconductor device including a leadframe and two stacked dies, a first of which is on a top surface of a leadframe while the second one is on a bottom surface of the leadframe. The drain region of the first die is coupled to a drain clip assembly that includes a drain clip that is in contact with a lead rail. The body of the semiconductor device includes a window or opening that exposes the drain region of the second die.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A multichip module is disclosed. In one embodiment, the multichip module includes a substrate having a first side and a second side, the first side being opposite to the first side. A driver chip is at the first side of the substrate. A semiconductor die comprising a vertical transistor is at the second side of the substrate. The driver chip and the semiconductor die are in electrical communication through the substrate.

Abstract: Increasing the number of MOSFET gate bump contacts makes MOSFET gate contacts more durable and reliable. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads overlying the source pad metallization reduces the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. The result is a reliable, durable MOSFET gate contact.

Abstract: A packaging arrangement for a semiconductor device including a leadframe and a die coupled thereto. The die is coupled to the leadframe such that its back surface (drain area) is coplanar with source leads and a gate lead extending from the leadframe. A stiffener is coupled to the leadframe and electrically isolated therefrom in order to help maintain the position of the source and gate pads of the leadframe. When the semiconductor device is coupled to a printed circuit board (PCB), the exposed surface of the die serves as the direct drain connections while the source leads and gate leads serve as the connections for the source and gate regions of the die.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: A carrier for use in a semiconductor die package is disclosed. In one embodiment, the carrier includes a die attach region and an edge region. A solder mask is on the edge region.

Abstract: Increasing the number of MOSFET gate bump contacts makes MOSFET gate contacts more durable and reliable. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads overlying the source pad metallization reduces the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. The result is a reliable, durable MOSFET gate contact.

Abstract: Careful repositioning of MOSFET gate contacts and increasing of their number makes MOSFET gate contacts more durable and reliable without requiring changes in either the leadframe design or the assembly process. Extension of the under-bump metal laterally from the gate contact with the gate pad metallization out to two or more gate pads not overlying the gate pad metallization minimizes the risk of delamination of the metallization due to thermal and mechanical stresses in assembly and operation. Use of more than one gate pad further reduces such failure risks. Positioning the gate pads sufficiently close to the original gate contact permits use of the same leadframe design and assembly process as would be used for a single gate pad placed directly over the gate contact. The result is a reliable, durable MOSFET gate contact compatible with current assembly methods.