Patents by Inventor Maria J. Anc

Maria J. Anc has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20090283743
    Abstract: A composite comprising a first layer comprising a first material including nanoparticles dispersed therein, wherein the first material comprises a material capable of transporting charge, a second layer comprising a second material, and a backing element that is removably attached to the uppermost layer of the composite or the lowermost layer of the composite. In certain preferred embodiments, a least a portion of the nanoparticles include a ligand attached to a surface thereof. Methods are also disclosed. Products including a composite is further provided. Composite materials can be particularly well-suited for use, for example, in products useful in various optical, electronic, optoelectronic, magnetic, or catalytic devices.
    Type: Application
    Filed: March 12, 2009
    Publication date: November 19, 2009
    Inventors: Seth Coe-Sullivan, Maria J. Anc, Jonathan S. Steckel
  • Publication number: 20090215208
    Abstract: Methods for depositing nanomaterial onto a substrate are disclosed. Also disclosed are compositions useful for depositing nanomaterial, methods of making devices including nanomaterials, and a system and devices useful for depositing nanomaterials.
    Type: Application
    Filed: October 6, 2008
    Publication date: August 27, 2009
    Inventors: Seth Coe-Sullivan, Maria J. Anc, LeeAnn Kim, John E. Ritter, Marshall Cox, Craig Breen, Vladimir Bulovic, Ioannis Kymissis, Robert F. Praino, JR., Peter T. Kazlas
  • Publication number: 20090215209
    Abstract: Methods for depositing material and/or nanomaterial are disclosed. Also disclosed are methods of making devices including nanomaterials, systems useful for depositing materials and/or nanomaterials, surface treated articles for depositing material and/or nanomaterial onto a substrate, and surface treated transfer surfaces.
    Type: Application
    Filed: October 7, 2008
    Publication date: August 27, 2009
    Inventors: Maria J. Anc, Seth Coe-Sullivan, LeeAnn Kim, Moungi G. Bawendi
  • Publication number: 20090208753
    Abstract: A method of depositing a nanomaterial onto a donor surface comprises applying a composition comprising nanomaterial to a donor surface. In another aspect of the invention there is provided a method of depositing a nanomaterial onto a substrate. Methods of making a device including nanomaterial are disclosed. An article of manufacture comprising nanomaterial disposed on a backing member is disclosed.
    Type: Application
    Filed: October 6, 2008
    Publication date: August 20, 2009
    Inventors: Seth Coe-Sullivan, Maria J. Anc, LeeAnn Kim, Vladimir Bulovic, Joannis Kymissis, John E. Ritter, Robert F. Praino, JR., Peter T. Kazlas, Seth Coe-Sullivan
  • Publication number: 20090181478
    Abstract: Methods for depositing material and nanomaterial onto a substrate are disclosed. Also disclosed are methods of making devices including nanomaterials, and a system useful for depositing materials and nanomaterials.
    Type: Application
    Filed: October 6, 2008
    Publication date: July 16, 2009
    Inventors: Marshall Cox, LeeAnn Kim, Craig Breen, Maria J. Anc, Seth Coe-Sullivan, Peter T. Kazlas
  • Patent number: 7173260
    Abstract: An ion implanter having a source, a workpiece support and a transport system for delivering ions from the source to an ion implantation chamber that contains the workpiece support. The implanter includes one or more removable inserts mounted to an interior of either the transport system or the ion implantation chamber for collecting material entering either the transport system or the ion implantation chamber due to collisions between ions and the workpiece within the ion implantation chamber during ion processing of the workpiece. A temperature control coupled to the one or more removable inserts for maintaining the temperature of the insert at a controlled temperature to promote formation of a film on said insert during ion treatment due to collisions between ions and said workpiece.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: February 6, 2007
    Assignee: Axcelis Technologies, Inc.
    Inventors: Maria J. Anc, Dale K. Stone, Christopher T. Reddy
  • Patent number: 6794264
    Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.
    Type: Grant
    Filed: April 30, 2002
    Date of Patent: September 21, 2004
    Assignee: Ibis Technology Corporation
    Inventors: Robert P. Dolan, Bernhardt F. Cordts, III, Maria J. Anc, Micahel L. Alles
  • Patent number: 6593173
    Abstract: Methods of producing buried insulating layers in semiconductor substrates are disclosed whereby a dose of selected ions is implanted into a substrate to form a buried precursor layer below an upper layer of the substrate, followed by oxidation of the substrate in an atmosphere having a selected oxygen concentration to form an oxide surface layer. The oxidation is performed at a temperature and for a time duration such that the formation of the oxide layer causes the injection of a controlled number of atoms of the substrate from a region proximate to an interface between the newly formed oxide layer and the substrate into the upper regions of the substrate to reduce strain. A high temperature annealing step is then performed to produce the insulating layer within the precursor layer.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: July 15, 2003
    Assignee: Ibis Technology Corporation
    Inventors: Maria J. Anc, Robert P. Dolan
  • Publication number: 20020123211
    Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.
    Type: Application
    Filed: April 30, 2002
    Publication date: September 5, 2002
    Applicant: IBIS TECHNOLOGY
    Inventors: Robert P. Dolan, Bernhardt F. Cordts, Maria J. Anc, Micahel L. Alles
  • Patent number: 6417078
    Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.
    Type: Grant
    Filed: December 21, 2000
    Date of Patent: July 9, 2002
    Assignee: Ibis Technology Corporation
    Inventors: Robert P. Dolan, Bernhardt F. Cordts, III, Maria J. Anc, Micahel L. Alles
  • Publication number: 20020081824
    Abstract: The present invention provides a method for creation of high quality semiconductor-on-insulator structures, e.g., silicon-on-insulator structures, using implantation of sub-stoichiometric doses of oxygen at multiple energies. The method employs sequential steps of ion implantation and high temperature annealing to produce structures with a top silicon layer having a thickness ranging from 10-250 nm and a buried oxide layer having a thickness 30-300 nm. The buried oxide layer has a breakdown field greater than 5 MV/cm. Further, the density of silicon inclusions in the BOX region is less than 2×107 cm−2. The process of the invention can be used to create an entire SOI wafer, or be used to create patterned SOI, regions where SOI regions are integrated with non-SOI regions.
    Type: Application
    Filed: December 21, 2000
    Publication date: June 27, 2002
    Applicant: Ibis Technology, Inc.
    Inventors: Robert P. Dolan, Bernhardt Cordts, Maria J. Anc, Michael L. Alles