Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes: first memory cells, first word lines, a first row decoder, and a driver circuit. The first row decoder includes first transistors capable of coupling the first word lines to first signal lines, and a first block decoder supplying a first block selection signal to the first transistors. When the controller issues a data read command, the first block decoder asserts the first block selection signal to allow the first transistors to transfer a first voltage to a selected first word line, and a second voltage to unselected other first word lines. After data is read, the first block decoder continues asserting the first block selection signal, and the driver circuit transfers a third voltage.

Abstract: According to an embodiment, a control circuitry performing: a first operation of reading data out of a memory cell with a first voltage applied to a word line while changing the first voltage by a first shift amount within a first range, and a second operation of reading data out of the memory cell with a second voltage applied to the word line while changing the second voltage by a second shift amount within a second range, wherein the second shift amount is smaller than the first shift amount, and wherein the control circuitry performs the second operation to apply the second voltage to the word line subsequently to application of the first voltage to the word line in the first operation.

Abstract: According to one embodiment, a nonvolatile memory includes: a memory cell array including memory cells; and a controller configured to execute a first refresh process on receiving a first command. The first refresh process includes reprogramming at least one second memory cell among first memory cells to which data has been programmed in a first group. In executing the first refresh process, the controller is configured to: select the second memory cell by verifying with a first voltage using a first amount in a case where the second memory cell has been programmed using the first voltage; and select the second memory cell by verifying with a second voltage using a second amount in a case where the second memory cell has been programmed using the second voltage.

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

Abstract: According to one embodiment, a magnetic memory puts a first magnetic domain having a magnetization direction which is the same as or opposite to a magnetic domain of a first layer of a magnetic memory line, into the first layer, based on a value of data and the magnetization direction of the first layer. When receiving a first command, the magnetic memory puts a first additional magnetic domain and a second additional magnetic domain having a magnetization direction opposite to the first additional magnetic domain into the magnetic memory line. When receiving a second command, the magnetic memory read the first and second additional magnetic domains to determine the magnetization direction of the first magnetic domain.

Abstract: A memory system includes a storage device and a controller. The storage device includes a first string including a first memory cell transistor and a second memory cell transistor connected in series to each other, and a first select transistor, a second string including a third memory cell transistor and a second select transistor, a gate of the second select transistor being independent from a gate of the first select transistor. The controller configured to perform first writing to cause a threshold voltage of the first memory cell transistor to be lower than a first target threshold voltage, perform second writing to cause a threshold voltage of the second memory cell transistor to be higher than a second target threshold voltage after the first writing, perform third writing to cause a threshold voltage of the first memory cell transistor to be higher than the first target threshold voltage after the second writing, and perform fourth writing on the third memory cell transistor after the third writing.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The first memory cell faces the second memory cell. When reading data from the first memory cell, the semiconductor memory device is configured to perform the first operation in which a first voltage is applied to the first word line and a second voltage higher than the first voltage is applied to the second word line, and perform the second operation in which a third voltage higher than the first voltage and a fourth voltage different from the third voltage are applied to the first word line and a fifth voltage lower than the second to the fourth voltage is applied to the second word line.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes first blocks each including magnetic memory lines and performs writing and reading of data for each block by a last-in first-out (LIFO) method by shifting, in a unit of a layer, data portions stored in a plurality of layers, respectively, in a first direction from a top layer to a last layer or in a second direction opposite to the first direction, the magnetic memory lines including the plurality of layers. The controller controls the nonvolatile memory. The controller selects a source block of a compaction process from the first blocks based on a ratio of layers of a second attribute to the plurality of layers in each of the first blocks.

Abstract: A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers are each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. The server generates list information including the target information from the first and second monitoring devices, and transmits the list information to the first and second monitoring devices. The first controller further generates a map according to the list information received from the server, and displays the map on the first display.