Patents by Inventor Mario Francisco Velez

Mario Francisco Velez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11616185
    Abstract: A device that includes a region comprising a heat generating device, and an energy harvesting device coupled to the region comprising the heat generating device. The energy harvesting device includes a first thermal conductive layer, a thermoelectric generator (TEG) coupled to the first thermal conductive layer, and a second thermal conductive layer coupled the thermoelectric generator (TEG) such that the thermoelectric generator (TEG) is between the first thermal conductive layer and the second thermal conductive layer. In some implementations, the energy harvesting device includes an insulation layer.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: March 28, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Jorge Luis Rosales, Victor Adrian Chiriac, Mario Francisco Velez, Peng Wang
  • Patent number: 11121699
    Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.
    Type: Grant
    Filed: February 19, 2019
    Date of Patent: September 14, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Kai Liu, Rui Tang, Changhan Hobie Yun, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20210257989
    Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.
    Type: Application
    Filed: April 30, 2021
    Publication date: August 19, 2021
    Inventors: Kai LIU, Rui TANG, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
  • Patent number: 11024454
    Abstract: Disclosed is an inductor device including a first curved metal plate, a second curved metal plate below and substantially vertically aligned with the first curved metal plate, and a first elongated via vertically aligned between the first curved metal plate and the second curved metal plate, the first elongated via configured to conductively couple the first curved metal plate to the second curved metal plate and having an aspect ratio of a width to a height of the first elongated via of at least approximately 2 to 1.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: June 1, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Niranjan Sunil Mudakatte, Jonghae Kim, Chengjie Zuo, David Francis Berdy
  • Patent number: 11003884
    Abstract: A fingerprint sensor device includes a sensor substrate, a plurality of sensor circuits over a first surface of the sensor substrate, and a transceiver layer located over the plurality of sensor circuits and the first surface of the sensor substrate. The transceiver layer includes a piezoelectric layer and a transceiver electrode positioned over the piezoelectric layer. The piezoelectric layer and the transceiver electrode are configured to generate one or more ultrasonic waves or to receive one or more ultrasonic waves. The fingerprint sensor device may include a cap coupled to the sensor substrate and a cavity formed between the cap and the sensor substrate. The cavity and the sensor substrate may form an acoustic barrier.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 11, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Nicholas Ian Buchan, Mario Francisco Velez, Chin-Jen Tseng, Hrishikesh Vijaykumar Panchawagh, Firas Sammoura, Jessica Liu Strohmann, Kostadin Dimitrov Djordjev, David William Burns, Leonard Eugene Fennell, Jon Gregory Aday
  • Patent number: 10944379
    Abstract: An integrated radio frequency (RF) circuit combines complementary features of passive devices and acoustic filters and includes a first die, a second die, and a third die. The first die includes a substrate having one or more passive devices. The second die includes a first acoustic filter. The second die is stacked and coupled to a first surface of the first die. The third die includes a second acoustic filter. The third die is stacked and coupled to a second surface opposite the first surface of the first die.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: March 9, 2021
    Assignee: Qualcomm Incorporated
    Inventors: David Francis Berdy, Changhan Hobie Yun, Shiqun Gu, Niranjan Sunil Mudakatte, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim
  • Publication number: 20200266512
    Abstract: Aspects of the disclosure are directed to a bandpass filter including a first, second, third and fourth resonators, wherein the second and third resonators are in parallel, wherein the first resonator includes a first and second terminals, wherein the second resonator includes a second resonator top terminal and a second resonator bottom terminal, wherein the third resonator includes a third resonator top terminal and a third resonator bottom terminal, wherein the fourth resonator includes a third terminal and a fourth terminal; wherein the first terminal is coupled to the second resonator top terminal, wherein the second terminal is coupled to the third resonator top terminal, wherein the third terminal is coupled to the third resonator bottom terminal, wherein the fourth terminal is coupled to the second resonator bottom terminal; a first inductor coupled to the first and third terminals; and a second inductor coupled to the second and fourth terminals.
    Type: Application
    Filed: February 19, 2019
    Publication date: August 20, 2020
    Inventors: Kai LIU, Rui TANG, Changhan Hobie YUN, Mario Francisco VELEZ, Jonghae KIM
  • Patent number: 10734332
    Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: August 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Bradley Lasiter, Ravindra Vaman Shenoy, Donald William Kidwell, Jr., Mohammad Ali Tassoudji, Vladimir Aparin, Seong Heon Jeong, Jeremy Dunworth, Alireza Mohammadian, Mario Francisco Velez, Chin-Kwan Kim
  • Patent number: 10685924
    Abstract: An package and related methods are disclosed. The package may include an antenna, an insert made of low-loss material, and a mold, wherein the mold directly contacts and surrounds at least a portion of the insert, wherein the antenna is formed of conductive material disposed at least in part on a surface of the insert.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: June 16, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Jon Bradley Lasiter, Ravindra Vaman Shenoy, Donald William Kidwell, Jr., Mohammad Ali Tassoudji, Mario Francisco Velez
  • Patent number: 10614942
    Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: April 7, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Mario Francisco Velez, Nosun Park, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Xiaoju Yu, Paragkumar Ajaybhai Thadesar, Jonghae Kim
  • Patent number: 10607980
    Abstract: A device includes a glass substrate and a capacitor. The capacitor includes a first metal coupled to a first electrode, a dielectric structure, and a via structure comprising a second electrode of the capacitor. The first metal structure is separated from the via structure by the dielectric structure.
    Type: Grant
    Filed: January 3, 2018
    Date of Patent: March 31, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Changhan Hobie Yun, Daeik Daniel Kim, Chengjie Zuo, David Francis Berdy, Mario Francisco Velez, Jonghae Kim
  • Publication number: 20200091094
    Abstract: A filter including an insulating die having a plurality of MIM (Metal Insulator Metal) capacitors disposed within the die is disclosed. A 2.5D (2.5 Dimensional) inductor disposed within a redistribution layer (RDL) is electrically coupled to at least one of the plurality of MIM capacitors in the die. A 3D (3 Dimensional) inductor is disposed around the die and is electrically coupled to at least one of the plurality of MIM capacitors.
    Type: Application
    Filed: September 14, 2018
    Publication date: March 19, 2020
    Inventors: Changhan Hobie YUN, Mario Francisco VELEZ, Nosun PARK, Niranjan Sunil MUDAKATTE, Wei-Chuan CHEN, Paragkumar Ajaybhai THADESAR, Christopher POLLOCK, Xiaoju YU, Rongguo ZHOU, Kai LIU, Jonghae KIM
  • Patent number: 10582609
    Abstract: A passive on glass (POG) on filter capping apparatus may include an acoustic filter die. The apparatus may further include a capping die electrically coupled to the acoustic filter die. The capping die may include a 3D inductor.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: March 3, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Changhan Hobie Yun, Jonghae Kim, Xiaoju Yu, Mario Francisco Velez, Wei-Chuan Chen, Niranjan Sunil Mudakatte, Matthew Michael Nowak, Christian Hoffmann, Rodrigo Pacher Fernandes, Manuel Hofer, Peter Bainschab, Edgar Schmidhammer, Stefan Leopold Hatzl
  • Patent number: 10553671
    Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.
    Type: Grant
    Filed: June 10, 2016
    Date of Patent: February 4, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez
  • Publication number: 20200020473
    Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.
    Type: Application
    Filed: July 13, 2018
    Publication date: January 16, 2020
    Inventors: Changhan Hobie YUN, Mario Francisco VELEZ, Nosun PARK, Wei-Chuan CHEN, Niranjan Sunil MUDAKATTE, Xiaoju YU, Paragkumar Ajaybhai THADESAR, Jonghae KIM
  • Patent number: 10498307
    Abstract: An integrated device that includes a substrate, a first interconnect over the substrate and a second interconnect comprising a first portion and a second portion. The integrated device further comprising a first dielectric layer between the first interconnect and the first portion of the second interconnect such that the first interconnect vertically overlaps with the first dielectric layer and the first portion of the second interconnect. The integrated device also includes a second dielectric layer formed over the substrate. The first interconnect, the first dielectric layer and the first portion of the second interconnect are configured to operate as a capacitor. The first portion and the second portion of the second interconnect are configured to operate as an inductor.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: December 3, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mario Francisco Velez, Niranjan Sunil Mudakatte, Jonghae Kim, Changhan Hobie Yun, David Francis Berdy, Shiqun Gu, Chengjie Zuo
  • Patent number: 10490621
    Abstract: Apparatus implementing various structures to decrease the distance between two inductive elements for tuning an inductance with greater variability (a wider tuning range). One example integrated circuit (IC) package generally includes a laminate, a solder resist layer disposed on an upper surface of the laminate, and a semiconductor die disposed above the laminate and comprising a first inductor. At least a portion of a second inductor is disposed above a section of the solder resist layer, the first inductor at least partially overlaps the second inductor, and there is a gap between the first inductor and the second inductor.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Paragkumar Ajaybhai Thadesar, Mario Francisco Velez, Changhan Hobie Yun, Francesco Carrara, Jonghae Kim, Xiaoju Yu, Niranjan Sunil Mudakatte
  • Patent number: 10490880
    Abstract: The disclosure relates to a glass-based antenna array package. In an aspect, such a glass-based antenna array package includes a single glass substrate layer, one or more antennas attached to a first side of the glass substrate layer, at least one semiconductor device attached to a second side of the glass substrate layer, and a first photoimageable dielectric layer adhered to the second side of the glass substrate layer and encapsulating the at least one semiconductor device. A method of manufacturing the same is also disclosed.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporation
    Inventors: Jon Bradley Lasiter, Ravindra Vaman Shenoy, Donald William Kidwell, Jr., Mohammad Ali Tassoudji, Mario Francisco Velez
  • Patent number: 10490348
    Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: November 26, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Mario Francisco Velez, Daeik Daniel Kim, Niranjan Sunil Mudakatte, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Yunfei Ma, Robert Paul Mikulka
  • Patent number: 10433425
    Abstract: A passive structure using conductive pillar technology instead of through via technology includes a substrate having a first redistribution layer (RDL) and a three-dimensional (3D) integrated passive device on the substrate. The passive structure includes multiple pillars on the substrate where each of the pillars is taller than the 3D integrated passive device. The passive structure further includes a molding compound on the substrate surrounding the 3D integrated passive device and the pillars. Furthermore, the passive structure includes multiple external interconnects coupled to the first RDL through the pillars.
    Type: Grant
    Filed: August 1, 2018
    Date of Patent: October 1, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Kai Liu, Changhan Hobie Yun, Jonghae Kim, Mario Francisco Velez