Patents by Inventor Mario Francisco Velez

Mario Francisco Velez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160095225
    Abstract: A semiconductor device includes a first integrated circuit chip, a second integrated circuit chip, a coupled inductor system, and a semiconductor package. The first integrated circuit chip is connected to a substrate and configured to process digital data. The second integrated circuit chip is configured to manage power for the first integrated circuit chip. The coupled inductor system is embedded in the substrate, connected to the second integrated circuit chip, and has a first inductor configured to be magnetically coupled to a second inductor. The semiconductor package is configured to encapsulate the first integrated circuit chip and the second integrated circuit chip.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Siamak FAZELPOUR, Mario Francisco VELEZ, Jiantao ZHENG
  • Publication number: 20160095208
    Abstract: A device includes a stress relief region between at least two stress domains of a substrate (e.g., of a semiconductor die or other integrated circuit). The stress relief region includes a conductive structure electrically coupling circuitries of the stress domains between which the conductive structure is disposed.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Daeik Daniel Kim, Je-Hsiung Jeffrey Lan, Changhan Hobie Yun, Mario Francisco Velez, Chengjie Zuo, Jonghae Kim, David Francis Berdy
  • Publication number: 20160093750
    Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.
    Type: Application
    Filed: September 26, 2014
    Publication date: March 31, 2016
    Inventors: Daeik Daniel Kim, Jonghae Kim, Chengjie Zuo, Sang-June Park, Changhan Hobie Yun, Mario Francisco Velez, David Francis Berdy, Matthew Michael Nowak, Robert Paul Mikulka
  • Patent number: 9275786
    Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
    Type: Grant
    Filed: July 18, 2014
    Date of Patent: March 1, 2016
    Assignee: QUALCOMM INCORPORATED
    Inventors: David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
  • Patent number: 9270254
    Abstract: Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.
    Type: Grant
    Filed: November 14, 2011
    Date of Patent: February 23, 2016
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventors: Chengjie Zuo, Changhan Yun, Chi Shun Lo, Wesley Nathaniel Allen, Mario Francisco Velez, Jonghae Kim, Sanghoon Joo
  • Patent number: 9264013
    Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: February 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Daeik Daniel Kim, Mario Francisco Velez, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Matthew Michael Nowak
  • Publication number: 20160020193
    Abstract: Some features pertain to an integrated device (e.g., package-on-package (PoP) device) that includes a substrate, a first die, a first encapsulation layer, a first redistribution portion, a second die, a second encapsulation layer, and a second redistribution portion. The substrate includes a first surface and a second surface. The substrate includes a capacitor. The first die is coupled to the first surface of the substrate. The first encapsulation layer encapsulates the first die. The first redistribution portion is coupled to the first encapsulation. The second die is coupled to the second surface of the substrate. The second encapsulation layer encapsulates the second die. The second redistribution portion is coupled to the second encapsulation layer.
    Type: Application
    Filed: July 17, 2014
    Publication date: January 21, 2016
    Inventors: Jong-Hoon Lee, Young Kyu Song, Daeik Daniel Kim, Jung Ho Yoon, Uei-Ming Jow, Mario Francisco Velez, Jonghae Kim, Xiaonan Zhang, Ryan David Lane
  • Publication number: 20160020013
    Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.
    Type: Application
    Filed: July 18, 2014
    Publication date: January 21, 2016
    Inventors: David Francis BERDY, Chengjie ZUO, Daeik Daniel KIM, Changhan Hobie YUN, Mario Francisco VELEZ, Robert Paul MIKULKA, Jonghae KIM
  • Publication number: 20160005715
    Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.
    Type: Application
    Filed: July 3, 2014
    Publication date: January 7, 2016
    Inventors: Siamak FAZELPOUR, Jiantao ZHENG, Mario Francisco VELEZ
  • Publication number: 20150371751
    Abstract: Methods and apparatuses, wherein the method forms a first plurality of vias in a substrate, further comprising forming the first plurality of vias to be substantially the same height. The method forms a plurality of conductive traces external to the substrate and couples the plurality of conductive traces to the first plurality of vias: wherein the plurality of conductive traces and the first plurality of vias comprise a plurality of conductive turns and wherein the plurality of conductive turns are in a spiral configuration substantially within a first plane.
    Type: Application
    Filed: June 24, 2014
    Publication date: December 24, 2015
    Inventors: Daeik Daniel KIM, Changhan Hobie YUN, Mario Francisco VELEZ, Chengjie ZUO, David Francis BERDY, Jonghae KIM
  • Patent number: 9203373
    Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: December 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Lan, Daeik D. Kim, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
  • Patent number: 9202789
    Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: December 1, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Chengjie Zuo, Changhan Hobie Yun, David Francis Berdy, Robert Paul Mikulka
  • Publication number: 20150334847
    Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 19, 2015
    Inventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
  • Publication number: 20150303148
    Abstract: Some novel features pertain to an integrated device package (e.g., die package) that includes a package substrate, a die, an encapsulation layer and a first set of metal layers. The package substrate includes a first surface and a second surface. The die is coupled to the first surface of the package substrate. The encapsulation layer encapsulates the die. The first set of metal layers is coupled to a first exterior surface of the encapsulation layer. In some implementations, the first set of metal layers is configured to operate as a die-to-wire connector of the integrated device package. In some implementations, the integrated device package includes a second set of metal layers coupled to the second surface of the package substrate. In some implementations, the integrated device package includes a second set of metal layers coupled to a second exterior surface of the encapsulation layer.
    Type: Application
    Filed: April 16, 2014
    Publication date: October 22, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Chengjie Zuo, Changhan Hobie Yun, David Francis Berdy, Robert Paul Mikulka
  • Publication number: 20150304059
    Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 22, 2015
    Inventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
  • Publication number: 20150287677
    Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.
    Type: Application
    Filed: September 11, 2014
    Publication date: October 8, 2015
    Inventors: Je-Hsiung Jeffrey LAN, David Francis BERDY, Chengjie ZUO, Daeik Daniel KIM, Changhan Hobie YUN, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA, Jonghae KIM
  • Publication number: 20150279920
    Abstract: Base pads are spaced by a pitch on a support surface. Conducting members, optionally Cu or other metal pillars, extend up from the base pads to top pads. A top pad interconnector connects the top pads in a configuration establishing an inductor current path between the base pads.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Chengjie ZUO, Jonghae KIM, Daeik Daniel KIM, Changhan Hobie YUN, Mario Francisco VELEZ
  • Publication number: 20150271920
    Abstract: Systems and methods relate to a semiconductor package comprising a first substrate or a 2D passive-on-glass (POG) structure with a passive component and a first set of one or more package pads formed on a face of a glass substrate. The semiconductor package also includes a second or laminate substrate with a second set of one or more package pads formed on a face of the second or laminate substrate. Solder balls are dropped, configured to contact the first set of one or more package pads with the second set of one or more package pads, wherein the first substrate or the 2D POG structure is placed face-up on the face of the second or laminate substrate. A printed circuit board (PCB) can be coupled to a bottom side of the second or laminate substrate.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 24, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Daeik Daniel KIM, Jonghae KIM, Chengjie ZUO, Changhan Hobie YUN, Mario Francisco VELEZ, Robert Paul MIKULKA
  • Patent number: 9136574
    Abstract: This disclosure provides systems, methods and apparatus for a compact 3-D coplanar transmission line (CTL). In one aspect, the CTL has a proximal end and a distal end separated, in a first plane, by a distance D, the first plane being parallel to a layout area of a substrate. The plane is defined by mutually orthogonal axes x and z The CTL provides a conductive path having pathlength L. D is substantially aligned along axis z, L is at least 1.5×D, and the CPW is configured such that at least one third of the pathlength L is disposed along one or more directions having a substantial component orthogonal to the first plane. Less than one third of the pathlength L is disposed in a direction having a substantial component parallel to axis x.
    Type: Grant
    Filed: June 10, 2013
    Date of Patent: September 15, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Daeik Daniel Kim, David Francis Berdy, Jonghae Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka
  • Publication number: 20150256143
    Abstract: An integrated circuit device includes a piezoelectric substrate having a first surface and a second surface opposite the first surface. The device also includes a first electrode and a second electrode on the first surface of the piezoelectric substrate, the first electrode having a first width and the second electrode having a second width. The device further includes a third electrode and a fourth electrode on the second surface of the piezoelectric substrate, the third electrode having a third width that is substantially the same as the second width, and the fourth electrode having a fourth width that is substantially the same as the first width. The first and third electrodes operate as part of a first portion of a microelectromechanical systems (MEMS) resonator, and the second and fourth electrodes operate as part of a second portion of the MEMS resonator.
    Type: Application
    Filed: March 4, 2014
    Publication date: September 10, 2015
    Applicant: QUALCOMM INCORPORATED
    Inventors: Changhan Hobie YUN, Chengjie ZUO, Jonghae KIM, Mario Francisco VELEZ, Daeik Daniel KIM, Rick Allen WILCOX