Patents by Inventor Mario Giuseppe Saggio

Mario Giuseppe Saggio has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11018008
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: May 25, 2021
    Assignee: STMICROELECTRONICS S.r.l.
    Inventors: Edoardo Zanetti, Simone Rascuná, Mario Giuseppe Saggio, Alfio Guarnera, Leonardo Fragapane, Cristina Tringali
  • Publication number: 20210151563
    Abstract: A MOSFET device includes a semiconductor body having a first and a second face. A source terminal of the MOSFET device includes a doped region which extends at the first face of the semiconductor body and a metal layer electrically coupled to the doped region. A drain terminal extends at the second face of the semiconductor body. The doped region includes a first sub-region having a first doping level and a first depth, and a second sub-region having a second doping level and a second depth. At least one among the second doping level and the second maximum depth has a value which is higher than a respective value of the first doping level and the first maximum depth. The metal layer is in electrical contact with the source terminal exclusively through the second sub-region.
    Type: Application
    Filed: November 12, 2020
    Publication date: May 20, 2021
    Inventors: Mario Giuseppe SAGGIO, Edoardo ZANETTI, Alfio GUARNERA
  • Publication number: 20210104445
    Abstract: An electronic power device includes a substrate of silicon carbide (SiC) having a front surface and a rear surface which lie in a horizontal plane and are opposite to one another along a vertical axis. The substrate includes an active area, provided in which are a number of doped regions, and an edge area, which is not active, distinct from and surrounding the active area. A dielectric region is arranged above the front surface, in at least the edge area. A passivation layer is arranged above the front surface of the substrate, and is in contact with the dielectric region in the edge area. The passivation layer includes at least one anchorage region that extends through the thickness of the dielectric region at the edge area, such as to define a mechanical anchorage for the passivation layer.
    Type: Application
    Filed: September 30, 2020
    Publication date: April 8, 2021
    Inventors: Simone RASCUNA', Claudio CHIBBARO, Alfio GUARNERA, Mario Giuseppe SAGGIO, Francesco LIZIO
  • Publication number: 20200373398
    Abstract: An electronic device comprising: a semiconductor body of silicon carbide, SiC, having a first and a second face, opposite to one another along a first direction, which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal, which extends at the first face of the semiconductor body; a second conduction terminal, which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer, of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.
    Type: Application
    Filed: May 22, 2020
    Publication date: November 26, 2020
    Inventors: Patrick FIORENZA, Fabrizio ROCCAFORTE, Mario Giuseppe SAGGIO
  • Publication number: 20200303564
    Abstract: A merged-PN-Schottky, MPS, diode includes an N substrate, an N-drift layer, a P-doped region in the drift layer, an ohmic contact on the P-doped region, a plurality of cells within the P-doped region and being portions of the drift layer where the P-doped region is absent, an anode metallization on the ohmic contact and on said cells, to form junction-barrier contacts and Schottky contacts respectively. The P-doped region has a grid-shaped layout separating from one another each cell and defining, together with the cells, an active area of the MPS diode. Each cell has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact extends at the doped region with continuity along the grid-shaped layout.
    Type: Application
    Filed: March 20, 2020
    Publication date: September 24, 2020
    Inventors: Simone RASCUNA', Mario Giuseppe SAGGIO
  • Publication number: 20200235248
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Application
    Filed: April 6, 2020
    Publication date: July 23, 2020
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNA'
  • Patent number: 10707202
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Grant
    Filed: July 3, 2018
    Date of Patent: July 7, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone Rascuná
  • Publication number: 20200176442
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Application
    Filed: February 3, 2020
    Publication date: June 4, 2020
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNÁ
  • Patent number: 10651319
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: May 12, 2020
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna'
  • Publication number: 20200044077
    Abstract: A MOSFET device comprising: a structural region, made of a semiconductor material having a first type of conductivity, which extends between a first side and a second side opposite to the first side along an axis; a body region, having a second type of conductivity opposite to the first type, which extends in the structural region starting from the first side; a source region, having the first type of conductivity, which extends in the body region starting from the first side; a gate region, which extends in the structural region starting from the first side, traversing entirely the body region; and a shielding region, having the second type of conductivity, which extends in the structural region between the gate region and the second side. The shielding region is an implanted region self-aligned, in top view, to the gate region.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 6, 2020
    Inventors: Mario Giuseppe Saggio, Edoardo Zanetti
  • Publication number: 20190214509
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Application
    Filed: March 18, 2019
    Publication date: July 11, 2019
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNA'
  • Publication number: 20190172715
    Abstract: A manufacturing method of an electronic device includes: forming a drift layer of an N type; forming a trench in the drift layer; forming an edge-termination structure alongside the trench by implanting dopant species of a P type; and forming a depression region between the trench and the edge-termination structure by digging the drift layer. The steps of forming the depression region and the trench are carried out at the same time. The step of forming the depression region comprises patterning the drift layer to form a structural connection with the edge-termination structure having a first slope, and the step of forming the trench comprises etching the drift layer to define side walls of the trench, which have a second slope steeper than the first slope.
    Type: Application
    Filed: December 4, 2018
    Publication date: June 6, 2019
    Inventors: Edoardo ZANETTI, Simone RASCUNÁ, Mario Giuseppe SAGGIO, Alfio GUARNERA, Leonardo FRAGAPANE, Cristina TRINGALI
  • Patent number: 10276729
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: April 30, 2019
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna′
  • Publication number: 20190013312
    Abstract: An integrated MOSFET device is formed in a body of silicon carbide and with a first type of conductivity. The body accommodates a first body region, with a second type of conductivity; a JFET region adjacent to the first body region; a first source region, with the first type of conductivity, extending into the interior of the first body region; an implanted structure, with the second type of conductivity, extending into the interior of the JFET region. An isolated gate structure lies partially over the first body region, the first source region and the JFET region. A first metallization layer extends over the first surface and forms, in direct contact with the implanted structure and with the JFET region, a JBS diode.
    Type: Application
    Filed: July 3, 2018
    Publication date: January 10, 2019
    Inventors: Mario Giuseppe SAGGIO, Simone RASCUNÁ
  • Patent number: 9911810
    Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.
    Type: Grant
    Filed: January 31, 2017
    Date of Patent: March 6, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Simona Lorenti, Cateno Marco Camalleri, Mario Giuseppe Saggio, Ferruccio Frisina
  • Publication number: 20170358690
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Application
    Filed: August 8, 2017
    Publication date: December 14, 2017
    Inventors: Mario Giuseppe Saggio, Simone Rascuna'
  • Patent number: 9748411
    Abstract: A switching device including: a body of semiconductor material, which has a first conductivity type and is delimited by a front surface; a contact layer of a first conductive material, which extends in contact with the front surface; and a plurality of buried regions, which have a second conductivity type and are arranged within the semiconductor body, at a distance from the contact layer.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: August 29, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna′
  • Patent number: 9711599
    Abstract: A switching device, such as a barrier junction Schottky diode, has a body of silicon carbide of a first conductivity type housing switching regions of a second conductivity type. The switching regions extend from a top surface of the body and delimit body surface portions between them. A contact metal layer having homogeneous chemical-physical characteristics extends on and in direct contact with the top surface of the body and forms Schottky contact metal portions with the surface portions of the body and ohmic contact metal portions with the switching regions. The contact metal layer is formed by depositing a nickel or cobalt layer on the body and carrying out a thermal treatment so that the metal reacts with the semiconductor material of the body and forms a silicide.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: July 18, 2017
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Mario Giuseppe Saggio, Simone Rascuna, Fabrizio Roccaforte
  • Publication number: 20170141191
    Abstract: Process for manufacturing a semiconductor power device, wherein a trench is formed in a semiconductor body having a first conductivity type; the trench is annealed for shaping purpose; and the trench is filled with semiconductor material via epitaxial growth so as to obtain a first column having a second conductivity type. The epitaxial growth is performed by supplying a gas containing silicon and a gas containing dopant ions of the second conductivity type in presence of a halogenide gas and occurs with uniform distribution of the dopant ions. The flow of the gas containing dopant ions is varied according to a linear ramp during the epitaxial growth; in particular, in the case of selective growth of the semiconductor material in the presence of a hard mask, the flow decreases; in the case of non-selective growth, in the absence of hard mask, the flow increases.
    Type: Application
    Filed: January 31, 2017
    Publication date: May 18, 2017
    Inventors: Simona Lorenti, Cateno Marco Camalleri, Mario Giuseppe Saggio, Ferruccio Frisina
  • Patent number: 9627472
    Abstract: An embodiment of a structure for a high voltage device of the type which comprises at least a semiconductor substrate being covered by an epitaxial layer of a first type of conductivity, wherein a plurality of column structures are realized, which column structures comprises high aspect ratio deep trenches, said epitaxial layer being in turn covered by an active surface area wherein said high voltage device is realized, each of the column structures comprising at least an external portion being in turn realized by a silicon epitaxial layer of a second type of conductivity, opposed than said first type of conductivity and having a dopant charge which counterbalances the dopant charge being in said epitaxial layer outside said column structures, as well as a dielectric filling portion which is realized inside said external portion in order to completely fill said deep trench.
    Type: Grant
    Filed: August 12, 2015
    Date of Patent: April 18, 2017
    Assignee: STMicroelectronics S.r.l.
    Inventors: Mario Giuseppe Saggio, Domenico Murabito, Angelo Magri'