Abstract: A method of sampling instructions executing in a multi-threaded processor which includes selecting an instruction for sampling, storing information relating to the instruction, determining whether the instruction includes an event of interest, and reporting the instruction if the instruction includes an event of interest on a per-thread basis. The event of interest includes information relating to a thread to which the instruction is bound.

Abstract: A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data item with the data type supported by the first destination to test a validity of the first instruction, and moving the first data item from the first source to the first destination based on the validity of the first instruction.

Abstract: A method for managing an object watchpoint during a garbage collection cycle, including identifying an object having a field, where the object is associated with an original object location, where the field is associated with an original field location, and where the object and the field are located in a memory heap of a virtual machine memory, setting, within a debugger, the object watchpoint on the original field location, where the object watchpoint is a memory trap associated with the object, determining, after a relocation of the object by a garbage collector (GC), a new object location associated with the object, determining a new field location of the field based on the new object location, and setting, within the debugger, the object watchpoint on the new field location.

Abstract: A method for implementing a just-in-time compiler involves obtaining high-level code templates in a high-level programming language, where the high-level programming language is designed for compilation to an intermediate language capable of execution by a virtual machine, and where each high-level code template represents an instruction in the intermediate language. The method further involves compiling the high-level code templates to native code to obtain optimized native code templates, where compiling the high-level code templates is performed, prior to runtime, using an optimizing static compiler designed for runtime use with the virtual machine. The method further involves implementing the just-in-time compiler using the optimized native code templates, where the just-in-time compiler is configured to substitute an optimized native code template when a corresponding instruction in the intermediate language is encountered at runtime.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: A system and method are provided for inlining across protection domain boundaries with a system virtual machine. A protection domain comprises a unique combination of a privilege level and a memory address space. The system virtual machine interprets or dynamically compiles not only application code executing under guest operating systems, but also the guest operating systems. For a program call that crosses a protection domain boundary, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the applicable protection domains. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions reveal the protection domain in which they are to operate, and instructions corresponding to different domains may be interleaved.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: A method for managing an object watchpoint during a garbage collection cycle, including identifying an object having a field, where the object is associated with an original object location, where the field is associated with an original field location, and where the object and the field are located in a memory heap of a virtual machine memory, setting, within a debugger, the object watchpoint on the original field location, where the object watchpoint is a memory trap associated with the object, determining, after a relocation of the object by a garbage collector (GC), a new object location associated with the object, determining a new field location of the field based on the new object location, and setting, within the debugger, the object watchpoint on the new field location.

Abstract: The present invention provides a system that facilitates performing concurrent garbage collection. During operation, the system executes a first mutator thread. While executing the first mutator thread, the system performs a garbage-collection operation using a garbage-collector thread. Performing the garbage-collection operation involves: discovering a live object in a from-space, which is being collected; creating a copy of the live object to a to-space, where live objects are copied to during garbage collection; and replacing the live object in the from-space with a forwarding pointer which points to a location of the copy of the live object in the to-space.

Abstract: One embodiment of the present invention provides a system that reduces the overhead involved in executing a native code method in an application running on a virtual machine. During operation, the system selects a call to a native code method to be optimized within the virtual machine, decompiles at least part of the native code method into an intermediate representation, and obtains an intermediate representation associated with the application. Next, the system combines the intermediate representation for the native code method with the intermediate representation associated with the application running on the virtual machine to form a combined intermediate representation, and generates native code from the combined intermediate representation, wherein the native code generation process optimizes interactions between the application running on the virtual machine and the native code method. A variation on this embodiment involves optimizing callbacks by the native code method into the virtual machine.

Abstract: By encoding an exception triggering value in storage referenced by an instruction in an otherwise unused slot (e.g., the delay slot of a delayed control transfer instruction or an unused instruction position in a VLIW-based architecture) coinciding with a safe point, an efficient coordination mechanism can be provided for multi-threaded code. Because the mechanism(s) impose negligible overhead when not employed and can be engaged in response to an event (e.g., a start garbage collection event), safe points can be defined at call, return and/or backward branch points throughout mutator code to reduce the latency between the event and suspension of all threads. Though particularly advantageous for thread suspension to perform garbage collection at safe points, the techniques described herein are more generally applicable to program suspension at coordination points coinciding with calls, returns, branches or calls, returns and branches therein.

Abstract: One embodiment of the present invention provides a system that accesses memory locations in an object-addressed memory system. During a memory access in the object-addressed memory system, the system receives an object identifier and an address. The system then uses the object identifier to identify a paged memory object associated with the memory access. Next, the system uses the address and a page table associated with the paged memory object to identify a memory page associated with the memory access. After determining the memory page, the system uses the address to access a memory location in the memory page.

Abstract: One embodiment of the present invention provides a system that facilitates in-cache reference counting in a cache memory. During operation, the system receives a command to update an old cache line with a new cache line. The system then determines if the new cache line is different than the old cache line. If so, the system determines if the old cache line contains any in-cache references. If so, for each such in-cache reference, the system decrements a reference counter in a cache line containing an object which is referenced by the in-cache reference. The system also determines if the new cache line contains any in-cache references. If so, for each such in-cache reference, the system increments a reference counter in a cache line containing an object which is referenced by the in-cache reference. Note that the reference counter in a cache line indicates a count of references in the cache that refer to an object contained in the cache line.

Abstract: One embodiment of the present invention provides a memory-management system that supports both address-referenced objects and identifier-referenced objects, wherein an address-referenced object is accessed through a reference containing an address of the object, and wherein an identifier-referenced object is accessed through a reference containing an object identifier (OID) for the object. During operation, the system receives a request to access an object. Next, the system determines if the object is an address-referenced object or an identifier-referenced object. If the object is an address-referenced object, the system accesses the object using the associated address for the object. If the object is an identifier-referenced object, the system accesses the object by using the associated OID for the object to look up the address for the object, and then using the address to access the object.

Abstract: Associating data source information with sampled runtime events allows identification of system components related to the sampled runtime events. Code can be optimized from the perspective of system components and for various architectures. A system provides a data source indication. The system associates the data source indication with a corresponding instruction instance. The instruction instance is related to a sampled runtime event, and the sampled runtime event is associated with the data source indication. The data source information and associated sampled runtime event can be supplied for profiling code.

Abstract: A system and method are provided for inlining a program call between processes executing under separate ISAs (Instruction Set Architectures) within a system virtual machine. The system virtual machine hosts any number of virtual operating system instances, each of which may execute any number of applications. The system virtual machine interprets or dynamically compiles not only application code executing under virtual operating systems, but also the virtual operating systems. For a program call that crosses ISA boundaries, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the virtual ISA of the code. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions are configured and executed (or emulated) to perform as they would within the virtual ISA.

Abstract: A system and method are provided for inlining across protection domain boundaries with a system virtual machine. A protection domain comprises a unique combination of a privilege level and a memory address space. The system virtual machine interprets or dynamically compiles not only application code executing under guest operating systems, but also the guest operating systems. For a program call that crosses a protection domain boundary, the virtual machine assembles an intermediate representation (IR) graph that spans the boundary. Region nodes corresponding to code on both sides of the call are enhanced with information identifying the applicable protection domains. The IR is optimized and used to generate instructions in a native ISA (Instruction Set Architecture) of the virtual machine. Individual instructions reveal the protection domain in which they are to operate, and instructions corresponding to different domains may be interleaved.

Abstract: One embodiment of the present invention provides a system that reduces coherence traffic in a multiprocessor system by supporting both coherent memory accesses and non-coherent memory accesses. During operation, the system receives a request to perform a memory access. Next, the system obtains a page table entry (PTE) associated with the memory access. The system then determines if the memory access is coherent or non-coherent by examining an indicator in the PTE. If the memory access is coherent, the system performs the memory access using a coherence protocol. On the other hand, if the memory access is non-coherent, the system performs the memory access without generating coherence traffic.

Abstract: A method for managing data, including obtaining a first instruction for moving a first data item from a first source to a first destination, determining a data type of the first data item, determining a data type supported by the first destination, comparing the data type of the first data item with the data type supported by the first destination to test a validity of the first instruction, and moving the first data item from the first source to the first destination based on the validity of the first instruction.

Abstract: One embodiment of the present invention provides a system that facilitates performing concurrent garbage collection. Note that the system uses hardware-supported GC barriers. During operation, the system executes a first mutator thread. While executing the first mutator thread, the system performs a garbage-collection operation using a garbage-collector thread. Performing the garbage-collection operation involves: discovering a live object in a from-space, which is being collected; creating a copy of the live object to a to-space, where live objects are copied to during garbage collection; and replacing the live object in the from-space with a forwarding pointer which points to a location of the copy of the live object in the to-space. Note that in some embodiments, the system marks cache lines comprising the live object in from-space as “forwarded,” which prevents any mutator threads from touching the cache lines.