Patents by Inventor Marius Cornea
Marius Cornea has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230376313Abstract: Techniques for instructions for min-max operations are described. An example apparatus comprises decoder circuitry to decode a single instruction, the single instruction to include fields for identifiers of a first source operand, a second source operand, an a destination operand, a field for an immediate operand, and a field for an opcode, the opcode to indicate execution circuitry is to perform a min-max operation, and execution circuitry to execute the decoded instruction according to the opcode to perform the min-max operation to determine a particular operation of five or more minimum and maximum operations in accordance with a value of the immediate operand, perform the determined particular operation on the identified first source operand and the identified second source operand to return a result, and store the result into the identified destination operand. Other examples are described and claimed.Type: ApplicationFiled: May 18, 2022Publication date: November 23, 2023Applicant: Intel CorporationInventors: Menachem Adelman, Amit Gradstein, Cristina Anderson, Marius Cornea-Hasegan
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Patent number: 10768896Abstract: An apparatus and method for performing a reciprocal. For example one embodiment of a processor comprises: a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal execution circuitry to execute the decoded reciprocal instruction, the reciprocal execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.Type: GrantFiled: December 21, 2017Date of Patent: September 8, 2020Assignee: Intel CorporationInventors: Cristina Anderson, Elmoustapha Ould-Ahmed-Vall, Marius Cornea-Hasegan, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
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Patent number: 10664237Abstract: An apparatus and method for performing a reciprocal square root. For example one embodiment of a processor comprises: a decoder to decode a reciprocal square root instruction to generate a decoded reciprocal square root instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal square root execution circuitry to execute the decoded reciprocal square root instruction, the reciprocal square root execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal square root execution circuitry to generate a reciprocal square root of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.Type: GrantFiled: December 21, 2017Date of Patent: May 26, 2020Assignee: Intel CorporationInventors: Cristina Anderson, Elmoustapha Ould-Ahmed-Vall, Marius Cornea-Hasegan, Robert Valentine, Mark Charney, Jesus Corbal, Venkateswara Madduri
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Publication number: 20190196790Abstract: An apparatus and method for performing a reciprocal square root. For example one embodiment of a processor comprises: a decoder to decode a reciprocal square root instruction to generate a decoded reciprocal square root instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal square root execution circuitry to execute the decoded reciprocal square root instruction, the reciprocal square root execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal square root execution circuitry to generate a reciprocal square root of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Cristina ANDERSON, Elmoustapha OULD-AHMED-VALL, Marius CORNEA-HASEGAN, Robert VALENTINE, Mark CHARNEY, Jesus CORBAL, Venkateswara MADDURI
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Publication number: 20190196789Abstract: An apparatus and method for performing a reciprocal. For example one embodiment of a processor comprises: a decoder to decode a reciprocal instruction to generate a decoded reciprocal instruction; a source register to store at least one packed input data element; a destination register to store a result data element; and reciprocal execution circuitry to execute the decoded reciprocal instruction, the reciprocal execution circuitry to use a first portion of the packed input data element as an index to a data structure containing a plurality of sets of coefficients to identify a first set of coefficients from the plurality of sets, the reciprocal execution circuitry to generate a reciprocal of the packed input data element using a combination of the coefficients and a second portion of the packed input data element.Type: ApplicationFiled: December 21, 2017Publication date: June 27, 2019Inventors: Cristina ANDERSON, Elmoustapha OULD-AHMED-VALL, Marius CORNEA-HASEGAN, Robert VALENTINE, Mark CHARNEY, Jesus CORBAL, Venkateswara MADDURI
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Patent number: 9996320Abstract: An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.Type: GrantFiled: December 23, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Patent number: 9996319Abstract: An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.Type: GrantFiled: December 23, 2015Date of Patent: June 12, 2018Assignee: Intel CorporationInventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Publication number: 20170185377Abstract: An example processor includes a register and an ADD low functional unit. The register stores first, second, and third floating point (FP) values. The ADD low functional unit receives a request to perform an ADD low operation and, responsive to the request: adds the first FP value with the second FP value to obtain a first sum value; rounds the first sum value to generate an ADD value; adds the first FP value with the second FP value to obtain a second sum value; subtracts the ADD value from the second sum value to generate a difference value; normalizes the difference value to obtain a normalized difference value; rounds the normalized difference value to generate an ADD low value; and sends the ADD low value to an application.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Publication number: 20170185379Abstract: An example processor includes a register and a fused multiply-add (FMA) low functional unit. The register stores first, second, and third floating point (FP) values. The FMA low functional unit receives a request to perform an FMA low operation: multiplies the first FP value with the second FP value to obtain a first product value; adds the first product with the third FP value to generate a first result value; rounds the first result to generate a first FMA value; multiplies the first FP value with the second FP value to obtain a second product value; adds the second product value with the third FP value to generate a second result value; and subtracts the FMA value from the second result value to obtain a third result value, which can then be normalized and rounded (FMA low result) and sent the FMA low result to an application.Type: ApplicationFiled: December 23, 2015Publication date: June 29, 2017Inventors: Cristina S. Anderson, Marius A. Cornea-Hasegan, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Nikita Astafev, Mark J. Charney, Milind B. Girkar, Amit Gradstein, Simon Rubanovich, Zeev Sperber
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Patent number: 8868632Abstract: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. An example apparatus obtains a first operand value and a second operand value. The example apparatus then determines if the second operand value subtracted from the first operand value is greater than a minimum value and determines if the first operand value is greater than a sum value associated with a minimum operand value. The example apparatus then asserts an output signal indicative of an absence of an underflow condition associated with a floating-point value based on conditions associated with determining whether the second operand value subtracted from the first operand value is greater than the minimum value and determining if the first operand value is greater than the sum value.Type: GrantFiled: September 15, 2005Date of Patent: October 21, 2014Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan
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Patent number: 8126954Abstract: Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware unit will generate an underflow condition. The operating of the plurality of comparator circuits and the logic devices involves inputting a multiply-add operation result value to at least some of the plurality of comparator circuits. In addition, a plurality of logic outputs are outputted via the plurality of logic devices. The plurality of logic outputs are indicative of comparison operations performed by at least some of the comparator circuits based on the multiply-add operation result value. An underflow indicator is outputted based on the plurality of logic outputs.Type: GrantFiled: July 31, 2009Date of Patent: February 28, 2012Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan
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Patent number: 8095586Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest away, producing positive result res1; and rounding the result res1 to precision P2 to the nearest away, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P2, the larger being res2, determining that rounding res0 to produce res1 involved rounding up, and decrementing the significand of res2 to obtain the corrected result.Type: GrantFiled: December 31, 2007Date of Patent: January 10, 2012Assignee: Intel CorporationInventor: Marius Cornea-Hasegan
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Patent number: 8069199Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest even, producing positive result res1; and rounding the result res1 to precision P2 to the nearest even, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P1, the larger (smaller) being res2, determining that rounding res0 to produce res1 involved rounding up (down), and decrementing (incrementing) the significand of res2 to obtain the corrected result res2?.Type: GrantFiled: December 31, 2007Date of Patent: November 29, 2011Assignee: Intel CorporationInventor: Marius Cornea-Hasegan
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Patent number: 7912890Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.Type: GrantFiled: May 11, 2006Date of Patent: March 22, 2011Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan
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Publication number: 20100300388Abstract: The object of the invention is to provide an economical vane-type camshaft adjuster system that meets the various requirements of various motors. For this purpose, according to the invention a modular system is provided for the valves of a vane-type camshaft adjuster system. Two different embodiments of valves are proposed. With one embodiment, a valve with mid-locking and without mid-locking may be constructed using the same bush. With the other embodiment, a valve with and without special utilization of the camshaft alternating torques may be constructed using the same bush.Type: ApplicationFiled: May 17, 2010Publication date: December 2, 2010Applicant: Hydraulik-Ring GmbHInventors: Matthias Lang, Marius Cornea
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Patent number: 7814138Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding addition results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.Type: GrantFiled: May 11, 2006Date of Patent: October 12, 2010Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan
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Patent number: 7707233Abstract: A machine-implemented method converts a number from a first base to a second base. Each one of a first group of machine operation computes a product whose factors include the number in the first base, and a previously calculated approximation to a respective negative power of the second base. A second group of machine operations are performed, each one using results of the first operations, to obtain further results. A respective one or more digits of the number in the second base is also determined, using each of these further results. Other embodiments are also described and claimed.Type: GrantFiled: May 19, 2005Date of Patent: April 27, 2010Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan
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Publication number: 20090292754Abstract: Methods and systems for detecting underflow in a floating-point operation are disclosed. In accordance with an example disclosed method a plurality of comparator circuits and a plurality of logic devices coupled to the plurality of comparator circuits are operated to determine whether performing a floating-point operation using a floating-point hardware unit will generate an underflow condition. The operating of the plurality of comparator circuits and the logic devices involves inputting a multiply-add operation result value to at least some of the plurality of comparator circuits. In addition, a plurality of logic outputs are outputted via the plurality of logic devices. The plurality of logic outputs are indicative of comparison operations performed by at least some of the comparator circuits based on the multiply-add operation result value. An underflow indicator is outputted based on the plurality of logic outputs.Type: ApplicationFiled: July 31, 2009Publication date: November 26, 2009Inventor: Marius A. Cornea-Hasegan
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Patent number: 7600531Abstract: The invention relates to a valve with a central guide and a check valve. The check valve and valve form an integrated component, the check valve being formed by a band which is shaped into a ring and is arranged in an internal groove.Type: GrantFiled: March 16, 2006Date of Patent: October 13, 2009Assignee: Hydraulik-Ring GmbHInventors: Helmut Patze, Marius Cornea, Uwe Paschen
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Patent number: 7593977Abstract: A method and system for determining whether a result d of a floating-point operation on operands a, b, c is tiny (may underflow) is disclosed. In one embodiment, a prediction whether d is tiny is made in hardware, but this prediction may include false results. Operands a, b, c are scaled to a?, b?, c? and then result d? from the floating-point operation on operands a?, b?, c? is calculated. A determination whether d will actually be tiny can be determined from the value of d?. A decision may then be made to proceed with either software or hardware calculations of d.Type: GrantFiled: December 23, 2002Date of Patent: September 22, 2009Assignee: Intel CorporationInventor: Marius A. Cornea-Hasegan