Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest even are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest even, producing positive result res1; and rounding the result res1 to precision P2 to the nearest even, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P1, the larger (smaller) being res2, determining that rounding res0 to produce res1 involved rounding up (down), and decrementing (incrementing) the significand of res2 to obtain the corrected result res2?.

Abstract: Methods and arrangements to correct for double rounding errors when rounding floating point numbers to nearest away are described. Embodiments include transformations, code, state machines or other logic to perform a floating point operation on one or more floating point numbers of precision P1 in base b, producing positive result res0 of precision greater than precision P1; rounding positive result res0 to precision P1 to the nearest away, producing positive result res1; and rounding the result res1 to precision P2 to the nearest away, where P2 is narrower than P1, producing result res2. The embodiments may also include correcting res2 for double rounding errors. The correcting may include determining that res1 is midway between two consecutive floating point numbers of precision P2, the larger being res2, determining that rounding res0 to produce res1 involved rounding up, and decrementing the significand of res2 to obtain the corrected result.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point additions and/or decimal fixed-point additions may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding addition results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: According to embodiments of the subject matter disclosed in this application, decimal floating-point multiplications and/or decimal fixed-point multiplications may be implemented using existing hardware for binary number operations. The implementation can be carried out in software, in hardware, or in a combination of software and hardware. Pre-calculated constants that are approximations to negative powers of 10 and stored in binary format may be used for rounding multiplication results to a designated precision by multiplying the results with a pre-calculated constant. Additionally, several parts of a decimal multiplication may be carried out in parallel. Furthermore, a simple comparison with a constant instead of an expensive remainder calculation may be used for midpoint detection and exactness determination.

Abstract: Methods and apparatus are disclosed for determining a floating-point exponent associated with an underflow condition or an overflow condition. The methods and apparatus determine the ‘true’ value of a floating-point exponent based on a truncated value of the floating-point exponent passed from a floating-point hardware unit to an exponent determination module when the floating-point hardware unit encounters an underflow condition or an overflow condition. The determined value of the floating-point exponent may then be passed to a floating-point software unit for additional floating-point calculations, if necessary. If the floating-point hardware unit does not encounter an underflow condition or an overflow condition, the floating-point hardware unit and/or the floating-point software unit preferably perform the floating-point operation without the assistance of the exponent determination module.

Abstract: Embodiments of a method and system for performing quad precision floating-point operations in a microprocessor are disclosed. In one embodiment, a method for calculating the square root of a number in a proposed revised IEEE 754 compliant 64-bit microprocessor comprises performing a single Newton-Raphson iteration in high precision to obtain an underestimate of the result, calculating and rounding the result using a simplified rounding method, and determining whether the result is inexact. In one embodiment, one or more operations of the method are performed using atomic microinstructions for execution in the microprocessor. The instructions store and manipulate the 128-bit quad precision operand using at least two floating-point registers, thus reducing latency in comparison to floating-point square root calculations that use the native instruction set of the microprocessor. Other embodiments are described and claimed.

Abstract: A machine-implemented method converts a number from a first base to a second base. Each one of a first group of machine operations computes a product whose factors include the number in the first base, and a previously calculated approximation to a respective negative power of the second base. A second group of machine operations are performed, each one using results of the first operations, to obtain further results. A respective one or more digits of the number in the second base is determined, using each of these further results. Other embodiments are also described and claimed.

Abstract: A bushing for a hydraulic valve has a bushing wall having openings allowing passage of a hydraulic medium to and from an interior of the bushing. The openings have an opening wall that at least across a portion of a circumference of the opening wall is formed as a molded bevel. The molded bevel is positioned at an acute angle to a radial plane of the bushing wall. The bushing wall has outer annular channels and the openings open into the outer annular channels, respectively.

Abstract: The invention relates to a valve with a central guide and a check valve. The check valve and valve form an integrated component, the check valve being formed by a band which is shaped into a ring and is arranged in an internal groove.

Abstract: A proportional solenoid valve or a camshaft adjusting device of motor vehicles has a valve housing and a piston movably arranged in the valve housing and provided with at least one pressure medium passage. A solenoid part is connected to the valve housing and acts on the piston. The valve housing has at least one working connector, a tank connector, and a pressure connector configured to supply a pressure medium into the piston. A leakage passage is provided that connects the pressure connector at all times to the at least one working connector.

Abstract: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. An example apparatus obtains a first operand value and a second operand value. The example apparatus then determines if the second operand value subtracted from the first operand value is greater than a minimum value and determines if the first operand value is greater than a sum value associated with a minimum operand value. The example apparatus then asserts an output signal indicative of an absence of an underflow condition associated with a floating-point value based on conditions associated with determining whether the second operand value subtracted from the first operand value is greater than the minimum value and determining if the first operand value is greater than the sum value.

Abstract: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. Preferably, the prediction is “pessimistic” in that it predicts that an underflow condition will result in all situations where an underflow condition might result. However, the methods and apparatus may also predict that an underflow condition might result in some situations where an underflow condition will not result. If an underflow condition is predicted, the floating-point multiply-add operation is preferably performed by a software routine capable of handling the underflow condition. If an underflow condition is not predicted, the floating-point multiply-add operation is preferably performed by a hardware circuit to increase speed and reduce computational overhead.

Abstract: A check valve is mounted in a valve arrangement having a valve member with an annular channel and at least one bore opening into the annular channel. The check valve has a closing element configured to close the at least one bore in the annular channel. The closing element is formed of a strip shaped as a ring. The strip of the check valve is arranged in the annular channel of the valve member.

Abstract: A valve has a valve housing having a flow path for a medium with at least one bore. At least one screen is arranged in the flow path of the medium in the valve housing. The screen is a perforated plate having screen openings and is made of a strap. The valve housing has at least one annular channel and the screen is arranged on a support surface provided in the annular channel.

Abstract: A bushing for a hydraulic valve has a bushing wall having openings allowing passage of a hydraulic medium to and from an interior of the bushing. The openings have an opening wall that at least across a portion of a circumference of the opening wall is formed as a molded bevel. The molded bevel is positioned at an acute angle to a radial plane of the bushing wall. The bushing wall has outer annular channels and the openings open into the outer annular channels, respectively.

Abstract: A proportional solenoid valve or a camshaft adjusting device of motor vehicles has a valve housing and a piston movably arranged in the valve housing and provided with at least one pressure medium passage. A solenoid part is connected to the valve housing and acts on the piston. The valve housing has at least one working connector, a tank connector, and a pressure connector configured to supply a pressure medium into the piston. A leakage passage is provided that connects the pressure connector at all times to the at least one working connector.

Abstract: A method and system for determining whether a result d of a floating-point operation on operands a, b, c is tiny (may underflow) is disclosed. In one embodiment, a prediction whether d is tiny is made in hardware, but this prediction may include false results. Operands a, b, c are scaled to a′, b′, c′ and then result d′ from the floating-point operation on operands a′, b′, c′ is calculated. A determination whether d will actually be tiny can be determined from the value of d′. A decision may then be made to proceed with either software or hardware calculations of d.

Abstract: A valve has a valve housing having a flow path for a medium with at least one bore. At least one screen is arranged in the flow path of the medium in the valve housing. The screen is a perforated plate having screen openings and is made of a strap. The valve housing has at least one annular channel and the screen is arranged on a support surface provided in the annular channel.

Abstract: Methods and apparatus for predicting an underflow condition associated with a floating-point multiply-add operation are disclosed. Preferably, the prediction is “pessimistic” in that it predicts that an underflow condition will result in all situations where an underflow condition might result. However, the methods and apparatus may also predict that an underflow condition might result in some situations where an underflow condition will not result. If an underflow condition is predicted, the floating-point multiply-add operation is preferably performed by a software routine capable of handling the underflow condition. If an underflow condition is not predicted, the floating-point multiply-add operation is preferably performed by a hardware circuit to increase speed and reduce computational overhead.

Abstract: Methods and apparatus are disclosed for determining a floating-point exponent associated with an underflow condition or an overflow condition. The methods and apparatus determine the ‘true’ value of a floating-point exponent based on a truncated value of the floating-point exponent passed from a floating-point hardware unit to an exponent determination module when the floating-point hardware unit encounters an underflow condition or an overflow condition. The determined value of the floating-point exponent may then be passed to a floating-point software unit for additional floating-point calculations, if necessary. If the floating-point hardware unit does not encounter an underflow condition or an overflow condition, the floating-point hardware unit and/or the floating-point software unit preferably perform the floating-point operation without the assistance of the exponent determination module.