Abstract: A signal generator 600 includes oscillator circuitry for generating first and second signals having a selected phase relationship and an interpolator 610 for interpolating between a phase of the first signal and a phase of the second signal to generate a third signal having a phase between the phases of the first and second signals.

Abstract: A system and method is disclosed for calibrating comparators of an ADC. Individual comparators may be calibrated at random or psuedo-random times while the ADC is performing conversions without the addition of extra "proxy" or replacement comparators. More particularly, at periodic intervals a psuedo-random one of the comparators may be disconnected from the standard ADC circuitry for calibration. In order to prevent a significant degradation in the conversion quality, the digital logic downstream of the comparators may be designed to provide the necessary adjustments to accommodate for the removal of one of the comparators. Thus, a calibration technique is provided in which individual comparators are removed from the data conversion path during conversion and the downstream logic adjusts to accommodate for the removal of the comparator. The calibration technique is particularly advantageous for use with optical data storage systems.

Abstract: A system and method is provided having a flash analog-to-digital converter (ADC) that includes an input signal buffer, a plurality of identical voltage comparators, and a reference generator. A clock signal defines the time instances at which the instantaneous input signal voltage is compared against a plurality of reference voltages generated by the reference generator. The individual comparator consists of a an integrating amplifier stage followed by an analog latching stage and a digital latch. The integrating amplifier input is allowed to track the input signal continuously. The amplifier output voltage is forced to a voltage close to zero before each conversion cycle is initiated by the ADC clock. At the beginning of the conversion cycle, the amplifier output is released and its voltage will follow an excursion related to the integral of the input of the amplifier. At a predefined time moment later, the analog latch is activated.

Abstract: A system and method for correcting comparator offsets which occur during operating conditions such that static and dynamic offsets are compensated is provided. The comparator may be calibrated for normal operating conditions. The calibration may be accomplished by providing adjustability of the comparators' threshold value and providing a feedback loop for adjusting the threshold value. In one preferred embodiment, the comparator may be utilized within a flash ADC, and in a more preferred embodiment, the comparator may be utilized within a flash ADC of a read/write channel circuit.