Patents by Inventor Marjan Radi

Marjan Radi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11934663
    Abstract: A client device includes at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other devices on a network each configured to provide a respective shared cache for the distributed cache. A Non-Volatile Memory express (NVMe) controller of the client device receives a command from a processor to access data in the shared cache and executes a program to use data read from the shared cache or data to be written to the shared cache to perform at least one computational operation. In another aspect, data is accessed in the shared cache using a kernel and data read from the shared cache or data to be written to the shared cache is used to perform at least one computational operation by the kernel.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: March 19, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Marjan Radi
  • Patent number: 11899585
    Abstract: A client device including at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other client devices on a network with each of the one or more other client devices configured to provide a respective shared cache for the distributed cache. At least one processor of the client device is configured to execute a kernel of an Operating System (OS) for allocating resources of the client device. The kernel is configured to access data for the distributed cache in the shared cache, which is located in a kernel space of the at least one memory.
    Type: Grant
    Filed: December 24, 2021
    Date of Patent: February 13, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventor: Marjan Radi
  • Publication number: 20240004795
    Abstract: A system includes at least one memory controller that partitions at least one memory into a plurality of nodes. Blast zones are formed that each include a predetermined number of nodes. Cache lines are erasure encoded to be stored in one or more blast zones with at least two nodes in a blast zone storing respective portions of a cache line and at least one node in the blast zone storing a parity portion. In one aspect, it is determined that data stored in one or more nodes of a blast zone needs to be reconstructed and stored in one or more spare nodes designated to replace the one or more nodes. Erasure decoding is performed using data from one or more other nodes in the blast zone to reconstruct the data for storage in the one or more spare nodes.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Dejan Vucinic, Jaco Hofmann, Paul Loewenstein, Huynh Tu Dang, Marjan Radi
  • Publication number: 20230418642
    Abstract: A Virtual Switching (VS) kernel module manages different flows of packets between at least one Virtual Machine (VM) running at a node and one or more other VMs running at the node or at one or more other nodes in a network. A packet is received from a first VM using the VS kernel module and is parsed to identify a memory message and an address for at least one memory block stored in a shared memory. At least one entry for the at least one memory block is updated in a directory in a kernel space using the VS kernel module based on the memory message. According to another aspect, a state for the at least one memory block is determined from the directory and the VS kernel module is used to respond to the memory request based on the determined state.
    Type: Application
    Filed: June 27, 2022
    Publication date: December 28, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230401079
    Abstract: A node includes a shared memory for a distributed memory system. A Virtual Switch (VS) controller establishes different flows of packets between at least one Virtual Machine (VM) running at the node and one or more other VMs running at the node or at another node. Requests to access the shared memory are queued in submission queues in a kernel space and processed requests are queued in completion queues in the kernel space. Indications of queue occupancy are determined for at least one queue and one or more memory request rates are set for at least one application based at least in part on the determined indications of queue occupancy. In another aspect, flow metadata is generated for each flow and at least one of the set one or more respective memory request rates and one or more respective resource allocations is adjusted for the at least one application.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230396561
    Abstract: A node includes a shared memory for a distributed memory system on a network. A Non-Volatile Memory express (NVMe) request is received from a user space application executed by a Virtual Machine (VM) to send an NVMe command to a different node in the network. If a data size for the NVMe request exceeds a maximum segment size of an NVMe over Fabric (NVMe-oF) connection, packets are created to be sent for the NVMe request and an order is determined for sending the packets with one or more packets including data for the NVMe command being sent before a last packet that includes the NVMe command. In another aspect, Virtual Switching (VS) queues are created in a kernel space with each VS queue corresponding to a different respective user space application initiating requests and at least one user space application being executed by one or more other nodes.
    Type: Application
    Filed: June 1, 2022
    Publication date: December 7, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230367713
    Abstract: A node includes at least one memory for use as a shared cache in a distributed cache. One or more other nodes on a network each provide a respective shared cache for the distributed cache. A request is received by a kernel of the node to access data in the shared cache and an Input/Output (I/O) queue is identified from among a plurality of I/O queues in a kernel space of the at least one memory for queuing the received request based on at least one of a priority indicated by the received request and an application that initiated the request. In another aspect, each I/O queue of the plurality of I/O queues corresponds to at least one of different respective priorities for requests to access data in the shared cache and different respective applications initiating requests to access data in the shared cache.
    Type: Application
    Filed: May 10, 2022
    Publication date: November 16, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11797379
    Abstract: A Non-Volatile Memory express (NVMe) node includes a memory used at least in part as a shared cache in a distributed cache. At least one processor of the NVMe node executes a kernel of an Operating System (OS). A request is received from another NVMe node to read data stored in the shared cache or to write data in the shared cache and an error detection operation is performed on the data for the request using the kernel. In another aspect, the kernel is used to perform Erasure Coding (EC) on data to be stored in the distributed cache. A network controller determines different EC ratios based at least in part on indications received from NVMe nodes of frequencies of access of different data and/or usage of the distributed cache by different applications. The network controller sends the determined EC ratios to the NVMe nodes.
    Type: Grant
    Filed: February 4, 2022
    Date of Patent: October 24, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11765250
    Abstract: A programmable switch includes ports, and circuitry to receive cache messages for a distributed cache from client devices. The cache messages are queued for sending to memory devices from the ports. Queue occupancy information is generated and sent to a controller that determines, based at least in part on the queue occupancy information, at least one of a cache message transmission rate for a client device, and one or more weights for the queues used by the programmable switch. In another aspect, the programmable switch extracts cache request information from a cache message. The cache request information indicates a cache usage and is sent to the controller, which determines, based at least in part on the extracted cache request information, at least one of a cache message transmission rate for a client device, and one or more weights for queues used in determining an order for sending cache messages.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: September 19, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230283618
    Abstract: A node includes a memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the node is configured to communicate with one or more other nodes in a network. Each of the one or more other nodes is configured to provide a respective shared cache for the distributed cache. At least one processor of the node is configured to execute a kernel of an Operating System (OS) for allocating resources of the node. The kernel is used to collect cache access information for the shared cache for identifying malicious operations in the distributed cache.
    Type: Application
    Filed: March 1, 2022
    Publication date: September 7, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11736417
    Abstract: A programmable switch includes a plurality of ports for communicating with devices on a network. Circuitry of the programmable switch is configured to receive a series of related messages from a first device on the network via at least one port, and determine whether one or more messages of the series of related messages have been received out-of-order based at least in part on a sequence number included in the one or more messages. The series of related messages are sent by the programmable switch to a second device via one or more ports in an order indicated by sequence numbers included in the series of related messages by delaying at least one message. According to one aspect, a network controller selects a programmable switch between the first device and the second device to serve as a message sequencer for reordering out-of-order messages using a stored network topology.
    Type: Grant
    Filed: February 12, 2021
    Date of Patent: August 22, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230251929
    Abstract: A Non-Volatile Memory express (NVMe) node includes a memory used at least in part as a shared cache in a distributed cache. At least one processor of the NVMe node executes a kernel of an Operating System (OS). A request is received from another NVMe node to read data stored in the shared cache or to write data in the shared cache and an error detection operation is performed on the data for the request using the kernel. In another aspect, the kernel is used to perform Erasure Coding (EC) on data to be stored in the distributed cache. A network controller determines different EC ratios based at least in part on indications received from NVMe nodes of frequencies of access of different data and/or usage of the distributed cache by different applications. The network controller sends the determined EC ratios to the NVMe nodes.
    Type: Application
    Filed: February 4, 2022
    Publication date: August 10, 2023
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20230221867
    Abstract: A client device includes at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other devices on a network each configured to provide a respective shared cache for the distributed cache. A Non-Volatile Memory express (NVMe) controller of the client device receives a command from a processor to access data in the shared cache and executes a program to use data read from the shared cache or data to be written to the shared cache to perform at least one computational operation. In another aspect, data is accessed in the shared cache using a kernel and data read from the shared cache or data to be written to the shared cache is used to perform at least one computational operation by the kernel.
    Type: Application
    Filed: January 10, 2022
    Publication date: July 13, 2023
    Inventor: Marjan Radi
  • Publication number: 20230205695
    Abstract: A client device including at least one memory configured to be used at least in part as a shared cache in a distributed cache. A network interface of the client device is configured to communicate with one or more other client devices on a network with each of the one or more other client devices configured to provide a respective shared cache for the distributed cache. At least one processor of the client device is configured to execute a kernel of an Operating System (OS) for allocating resources of the client device. The kernel is configured to access data for the distributed cache in the shared cache, which is located in a kernel space of the at least one memory.
    Type: Application
    Filed: December 24, 2021
    Publication date: June 29, 2023
    Inventor: Marjan Radi
  • Patent number: 11675706
    Abstract: A programmable switch includes at least one memory configured to store a cache directory for a distributed cache, and circuitry configured to receive a cache line request from a client device to obtain a cache line. The cache directory is updated based on the received cache line request, and the cache line request is sent to a memory device to obtain the requested cache line. An indication of the cache directory update is sent to a controller for the distributed cache to update a global cache directory. In one aspect, the controller sends at least one additional indication of the update to at least one other programmable switch to update at least one backup cache directory stored at the at least one other programmable switch.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: June 13, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11656992
    Abstract: A programmable switch receives a cache line request from a client of a plurality of clients on a network to obtain a cache line. One or more additional cache lines are identified based on the received cache line request and prefetch information. The cache line and the one or more additional cache lines are requested from one or more memory devices on the network. The requested cache line and the one or more additional cache lines are received from the one or more memory devices, and are sent to the client.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: May 23, 2023
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20220407625
    Abstract: A programmable switch includes a plurality of ports for communicating with a plurality of network devices. A packet for a distributed system is received via a port and at least one indicator is identified in the received packet. Reliability metadata associated with a network device used for the distributed system is generated using the at least one indicator. The generated reliability metadata is sent to a controller for the distributed system for predicting or determining a reliability of at least one of the network device and a communication link for the network device and the programmable switch.
    Type: Application
    Filed: June 21, 2021
    Publication date: December 22, 2022
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20220385732
    Abstract: A programmable switch includes ports to communicate with nodes including at least one node providing a cache accessible by other nodes. The programmable switch inspects received packets to identify information related to the cache. One or more cache metrics are determined for the cache based on the identified information and at least a portion of the cache is allocated to at least one application executed by at least one of the nodes based on the one or more cache metrics. According to one aspect, a distributed cache is formed of caches stored at nodes. The network controller stores distributed cache metrics and receives cache metrics from programmable switches for the caches to update the distributed cache metrics. Portions of the distributed cache are allocated to different applications based on the updated distributed cache metrics.
    Type: Application
    Filed: May 26, 2021
    Publication date: December 1, 2022
    Inventors: Marjan Radi, Dejan Vucinic
  • Patent number: 11503140
    Abstract: A programmable network interface for a server includes at least one memory storing connection parameters for previously active Non-Volatile Memory express over Fabric (NVMeoF) connections with different NVMe nodes. An NVMeoF connection request is received from an NVMe node, and it is determined whether the NVMe node is associated with connection parameters stored in the at least one memory. In response to determining that the NVMe node is associated with connection parameters stored in the at least one memory, a new NVMeoF connection is established for communicating with the NVMe node using the stored connection parameters. In one aspect, an address space of the server is partitioned, and an NVMe request queue is assigned to each partition of the address space. At least one address is identified in a received NVMeoF message, and an NVMe request queue is determined for performing an NVMe request included in the NVMeoF message.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: November 15, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Marjan Radi, Dejan Vucinic
  • Publication number: 20220200867
    Abstract: A programmable switch includes ports configured to communicate with Non-Volatile Memory express (NVMe) nodes. The programmable switch is configured to store a mapping of NVMe namespaces to physical storage locations located in the NVMe nodes. An NVMe node is determined by the programmable switch to have become inactive, and one or more NVMe namespaces are removed from the mapping that are associated with one or more physical storage locations in the inactive NVMe node. A notification of the one or more removed NVMe namespaces is sent to a network controller. According to one aspect, the network controller stores a global mapping of NVMe namespaces to physical storage locations in the NVMe nodes. The network controller sends at least one notification of the update to at least one other programmable switch to update at least one mapping stored at the at least one other programmable switch.
    Type: Application
    Filed: February 12, 2021
    Publication date: June 23, 2022
    Inventors: Marjan Radi, Dejan Vucinic