Patents by Inventor Mark A. Durlam

Mark A. Durlam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5768183
    Abstract: A plurality of layers of magnetic material are stacked in parallel, overlying relationship and separated by layers of non-magnetic material so as to form a multi-layer magnetic memory cell. The width of the cell is less than a width of magnetic domain walls within the magnetic layers so that magnetic vectors in the magnetic layers point along a length of the magnetic layers, and the ratio of the length to the width of the magnetic memory cell is in a range of 1.5 to 10. The magnetic layers are antiferromagnetically coupled when the ratio is less than 4 and ferromagnetically coupled when the ratio is greater than 4.
    Type: Grant
    Filed: September 25, 1996
    Date of Patent: June 16, 1998
    Assignee: Motorola, Inc.
    Inventors: Xiaodong T. Zhu, Saied N. Tehrani, Mark Durlam, Eugene Chen
  • Patent number: 5733827
    Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing first cap and etch stop layers and second cap and etch stop layers with a contact layer thereon so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually etched to define an electrode contact area and to expose the inter-electrode surface area. Portions of the first etch stop and cap layers remaining in the contact area are selectively removed and a metal contact is formed in the contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: March 31, 1998
    Assignee: Motorola, Inc.
    Inventors: Saied N. Tehrani, Mark Durlam, Marino J. Martinez, Jenn-Hwa Huang, Ernie Schirmann
  • Patent number: 5734606
    Abstract: New types of memory cell structures (20, 40) for a magnetic random access memory are provided. A memory cell (20, 40) has a plurality of cell pieces (21-24) where digital information is stored. Each cell piece is formed by magnetic layers (27, 28) separated by a conductor layer (29). A word line (25, 41) is placed adjacent each cell piece for winding around cell pieces (21-24) and meandering on a same plane on cell pieces (21-24), for example. The invention attains less power consumption and effective usage for a word current.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 31, 1998
    Assignee: Motorola, Inc.
    Inventors: Saied N. Tehrani, Eugene Chen, Ronald N. Legge, Xiaodong T. Zhu, Mark Durlam
  • Patent number: 5719088
    Abstract: A method of fabricating semiconductor devices with a passivated surface includes providing a contact layer on a substrate so as to define an inter-electrode surface area. A first layer and an insulating layer, which are selectively etchable relative to each other and to the substrate and the contact layer, are deposited on the contact layer and the inter-electrode surface area. The insulating layer and the first layer are individually and selectively etched to define an electrode contact area and to expose the inter-electrode surface area. The exposed inter-electrode surface area is passivated, either subsequent to or during the etching of the first layer. A metal contact is formed in the electrode contact area in abutting engagement with the insulating layer so as to seal the inter-electrode surface area.
    Type: Grant
    Filed: November 13, 1995
    Date of Patent: February 17, 1998
    Assignee: Motorola, Inc.
    Inventors: Jenn-Hwa Huang, Mark Durlam, Marino J. Martinez, Ernie Schirmann, Saied N. Tehrani, William J. Ooms
  • Patent number: 5703805
    Abstract: A method for detecting and storing four states contained in a MRAM cell having two layers (11,13) which have different thicknesses is provided. A first magnetic field is applied to the MRAM cell, which causes a magnetoresistive change in the MRAM cell. A first and second states are detected based on the magnetoresistive change. A second magnetic field is further applied to the MRAM cell. A third and fourth states are detected based on the magnetoresistive change due to the second magnetic field.
    Type: Grant
    Filed: May 8, 1996
    Date of Patent: December 30, 1997
    Assignee: Motorola
    Inventors: Saied N. Tehrani, Eugene Chen, Mark Durlam, Xiaodong T. Zhu
  • Patent number: 5699293
    Abstract: A magnetic random access memory device (10) has a plurality of pairs of memory cells (21a,21b), a column decoder (31), a row decoder (32), and a comparator (60). The pair of memory cells (21a,21b) is designated by column decoder (31) and row decoder (32) in response to a memory address. Complementary bits ("0" and "1") are stored in the pair of memory cells (21a,21b). When the state in the pair of memory cell (21a,21b) is read, both bits in the pair of memory cells (21a,21b) are compared to produce an output at one read cycle time to a bit line (70). This memory device omits a conventional auto-zeroing step so that a high speed MRAM device can be attained.
    Type: Grant
    Filed: October 9, 1996
    Date of Patent: December 16, 1997
    Assignee: Motorola
    Inventors: Saied N. Tehrani, Xiaodong T. Zhu, Eugene Chen, Mark Durlam
  • Patent number: 5659499
    Abstract: A magnetic memory utilizes a magnetic material to concentrate a magnetic field in a magnetic memory cell element. The magnetic material reduces the amount of current required to read and write the magnetic memory.
    Type: Grant
    Filed: November 24, 1995
    Date of Patent: August 19, 1997
    Assignee: Motorola
    Inventors: Eugene Chen, Saied N. Tehrani, Mark Durlam, Xiaodong T. Zhu
  • Patent number: 5512518
    Abstract: A manufacturable III-V semiconductor structure having small geometries is fabricated. A silicon nitride layer is formed on a III-V semiconductor material and a dielectric layer comprised of aluminum is formed on the silicon nitride layer. Another dielectric layer comprised of silicon and oxygen is formed over the dielectric layer comprised of aluminum. The dielectric layer comprised of aluminum acts as an etch stop for the etching of the dielectric layer comprised of silicon and oxygen with a high power reactive ion etch. The dielectric layer comprised of aluminum may then be etched with a wet etchant which does not substantially etch the silicon nitride layer. Damage to the surface of the semiconductor material by exposure to the high power reactive ion etch is prevented by forming the dielectric layer comprised of aluminum between the silicon nitride layer and the dielectric layer comprised of silicon and oxygen.
    Type: Grant
    Filed: June 6, 1994
    Date of Patent: April 30, 1996
    Assignee: Motorola, Inc.
    Inventors: Jaeshin Cho, Kelly W. Kyler, Wayne A. Cronin, Mark Durlam, Jonathan K. Abrokwah