Abstract: A technique facilitates controlled creation of pressure waves in a downhole environment. The technique enables creation of, for example, dynamic underbalance (DUB) pressure waves or dynamic overbalance (DOB) pressure waves which can be used to perform desired activities downhole. According to an embodiment, a pump is coupled with a pressure chamber and conveyed downhole into a borehole to a desired location. The pump may be operated downhole to change a pressure level in the pressure chamber until a sufficient pressure differential exists between an interior and an exterior of the pressure chamber. A release mechanism in communication with the pressure chamber is then rapidly opened to establish the desired pressure wave as the differing pressures equalize.

Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming, a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Abstract: A semiconductor device includes CMP dummy tiles (36) that are converted to active tiles by forming well regions (42) at a top surface of the dummy tiles, forming silicide (52) on top of the well regions, and forming a metal interconnect structure (72, 82) in contact with the silicided well tie regions for electrically connecting the dummy tiles to a predetermined supply voltage to provide latch-up protection.

Abstract: A flexible insert or guard has an elongated plastic body having a length to cover an opening of an electrical box and having two prongs or posts extending outwardly from the body for insertion into spaced apart mounting holes of the electrical box. The elongated plastic body flares outwardly at its ends in a region of the prongs and narrows along a center section to provide a gap between the insert and side walls of said electrical box wide enough to allow the insert to be removed after drywall is installed.

Abstract: A flexible insert or guard has an elongated plastic body having a length to cover an opening of an electrical box and having two prongs or posts extending outwardly from the body for insertion into spaced apart mounting holes of the electrical box. The elongated plastic body flares outwardly at its ends in a region of the prongs and narrows along a center section to provide a gap between the insert and side walls of said electrical box wide enough to allow the insert to be removed after drywall is installed.

Abstract: A data processor (10) has a branch target address cache (48) for storing the target addresses of a number of recently taken branch instructions. Normally, each fetch address is compared to the contents of the branch target address cache. If a hit occurs, then the data processor branches to the cached target address. The data processor also has a dispatch unit (60) that invalidates the data stored in the branch target address cache if and when it determines that the branch target address cache "hit" on an instruction that was not a branch instruction at all, a "phantom branch." The data processor thereby automatically invalidates its branch target address cache data after a context switch.

Abstract: The disclosed data processor (10) dispatches load/store multiple and load/store string instructions to a load/store unit (28) as a sequence of simple load or store instructions. The sequencer unit (18) assigns an entry of a rename buffer (34) to which the load/store unit writes back the data of each simple load instruction. This strategy facilitates early data forwarding for subsequent instructions. Conversely, the sequencer unit supplies a rename buffer tag to the load/store unit if it is not able to supply the operands of a simple store instruction.