Abstract: Apparatus and method for data management in a memory, such as but not limited to a flash memory array. In accordance with some embodiments, a plurality of data sets in a memory are identified as having a common data content and different physical addresses in the memory. A selected one of the data sets is marked as valid data and the remaining data sets are marked as stale data responsive to evaluation of at least one variable parameter associated with the physical addresses at which the data sets are respectively stored.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a first block of data is written to a group of memory cells at a first memory location in single-level cell (SLC) mode. The first block of data is copied from the first memory location to a group of memory cells at a second memory location to provide a backup copy of the first block of data during a protected mode of operation. A second block of data is subsequently overwritten to the group of memory cells at the first memory location so that the first memory location stores both the first and second blocks of data in multi-level cell (MLC) mode.

Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.

Abstract: An apparatus includes a controller capable of being coupled to a host interface and a memory device. The memory device includes two or more non-hierarchical, non-volatile memory units having different minimum addressable data unit sizes. The controller is configured to at least perform determining a workload indicator of a data object being stored in the memory device via the host interface. The controller selects one of the memory units in response to the workload indicator of the data object corresponding to the minimum addressable data unit size of the selected memory unit corresponding to the workload indicator. The data object is stored in the selected memory unit in response thereto.

Abstract: An incremental signal is defined that includes at least one of a duration and a peak voltage that is less than a respective minimum programming time or minimum programming voltage step of a resistive memory element. A characterization procedure is repeatedly performed that at least involves: applying a signal to the memory element, the signal being incremented by the incremental signal during each subsequent application; measuring a first resistance of the memory element in response to the signal; and c) measuring a second resistance of the memory element after a time period has elapsed from the measurement of the first resistance with no programming signal applied. In response to the first and second resistance measurements of the characterization procedure, a characterization parameter of the memory element is formed.

Abstract: Quality of service indicators are provided from a host via a host interface. The quality of service indicators relate to data stored in a non-volatile data storage via the host. Workload indicators related to the quality of service indicators are measured, and a weighting is assigned to the host in response to a correlation between the quality of service indicators and the measured workload indicators. The weighting is applied to the quality of service indicators when responding to data access requests from the host.

Abstract: Various embodiments may generally be directed to a variable resistance data storage device and a method of managing the device. A data storage device may have at least a controller configured to re-characterize at least one variable resistance memory cell in response to an identified variance from a predetermined resistance threshold.

Abstract: A data storage device may generally be constructed and operated with at least a controller configured to identify a variance from a predetermined threshold in at least one variable resistance memory cell and upgrade a first error correction code (ECC) level to a second ECC level for the at least one variable resistance memory cell.

Abstract: Method and apparatus for managing data in a cloud computing environment. In accordance with some embodiments, data updates are received to a multi-tier memory structure across a cloud network and stored as working data in an upper rewritable non-volatile memory tier of the memory structure. The working data are periodically logged to a lower non-volatile memory tier in the memory structure while a current version of the working data remain in the upper memory tier. The upper and lower memory tiers each are formed of rewritable memory cells having different constructions and storage attributes.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, metadata updates are stored in a first tier of a a multi-tier non-volatile memory structure responsive to access operations associated with data objects in the memory structure. The stored metadata updates are logged in a second, lower tier of the memory structure. The stored metadata updates are further migrated to a different location within the first tier responsive to an accumulated count of said access operations.

Abstract: Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with various embodiments, data are stored in a first location in a memory, and read from the first location a selected number of times. At least one parameter associated with the first location is measured after the data are read the selected number of times. The data are thereafter migrated to a second location in the memory responsive to the measured parameter indicating a presence of read disturbance in the data in the first location.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a first data object and an associated first ECC data set are generated and stored in a non-volatile (NV) main memory responsive to a first set of data blocks having a selected logical address. A second data object and an associated second ECC data set are generated responsive to receipt of a second set of data blocks having the selected logical address. The second data object and the second ECC data set are subsequently stored in the in the NV main memory responsive to a mismatch between the first ECC data set and the second ECC data set.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, input write data having a selected logical address are stored in a rewriteable non-volatile (NV) buffer. A copy of the input write data is transferred to an NV main memory using a sloppy write process. A verify operation is subsequently performed to verify successful transfer of the copy of the input write data to the NV main memory using a hash value generated responsive to the input write data in the NV buffer.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure. A metadata unit is generated to describe the data object, the metadata unit having a selected granularity. The metadata unit is stored in a different, second non-volatile tier of the multi-tier memory structure responsive to the selected granularity.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a first tier of a multi-tier memory structure is arranged into a plurality of garbage collection units (GCUs). Each GCU is formed from a plurality of non-volatile memory cells, and is managed as a unit. A plurality of data sets is stored in a selected GCU. A garbage collection operation is performed upon the selected GCU by identifying at least one of the plurality of data sets as a valid data set, migrating the valid data set to a non-volatile second tier of the multi-tier memory structure, and invalidating a programmed state of each of the plurality of non-volatile memory cells to prepare the selected GCU for storage of new data. In some embodiments, the invalidating operation involves setting all of the memory cells in the selected GCU to a known storage state.

Abstract: Parameters indicative of resistance variance of the memory elements are tracked. The resistance variance affects values of data stored in the resistance-based memory elements. A hash function is performed for each memory element. The hash function returns a reference to one of a plurality of counter elements. A value of each counter element is modified in response to the tracked parameter data of the associated memory element. Read operations affecting the memory elements are adjusted based on the values for the associated counter elements.

Abstract: A data storage device may generally be constructed and operated with at least one variable resistance memory cell configured with non-factory operational parameters by a controller. The non-factory operational parameters are assigned in response to an identified variance from a predetermined threshold in at least one variable resistance memory cell.

Abstract: Method and apparatus for managing data in a memory. In accordance with some embodiments, a data object is stored in a first non-volatile tier of a multi-tier memory structure. An ECC data set adapted to detect at least one bit error in the data object during a read operation is generated. The ECC data set is stored in a different, second non-volatile tier of the multi-tier memory structure.

Abstract: Method and apparatus for enhancing reliability and integrity of data stored in a non-volatile memory, such as in a solid-state drive (SSD) having an array of flash memory cells. In accordance with various embodiments, a controller is adapted to harden data stored in a first location of said memory in relation to a detected loss of retention characteristics of the first location. In some embodiments, the data are hardened by storing redundancy information associated with said data in a second location of said memory. The redundancy information can be a redundant set of the data or higher level error correct codes (ECC). The hardened data can be recovered to the host during a read operation by accessing the data stored in both the first and second locations.

Abstract: Data stripes and addressing for flash memory devices are provided. Flash memory devices illustratively have a plurality of programmable devices that are capable of simultaneously storing data. A plurality of erasure blocks are within each of the programmable devices, and each erasure block has pages of transistors. The flash memory devices are logically organized as a plurality of stripes. Each stripe has a height and a width. In an embodiment, the stripe height is greater than one page. In another embodiment, the stripe width is less than all of the programmable devices within the flash memory device.